IP Library Granted Patent US 9,214,431
Granted Patent B1
US 9,214,431 · App. 11/420,461 · Granted Dec 15, 2015

On-chip/off-chip magnetic shielding loop

Inventor: Manolis Terrovitis (Santa Clara, CA)
Assignee: QUALCOMM Incorporated
H01L23/552H01L2924/3025
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Quick Facts
Patent No.
US 9,214,431
App. No.
11/420,461
Granted
Dec 15, 2015
Kind
B1
Abstract

Magnetic coupling of noise sources can have a negative impact on the net performance of sensitive circuits. A magnetic shielding loop can advantageously minimize magnetic coupling associated with a circuit on an integrated circuit (IC) by including on-chip components, off-chip components, and interface components connecting the on-chip and off-chip components. The components can include conductive paths and contact pads on a die, package, and printed circuit board. The magnetic shielding loop magnetically isolates at least one of input terminals and noise-generating elements of the circuit.

Claims (33)

1. A structure minimizing magnetic coupling associated with a circuit on an integrated circuit, the structure comprising:

on-chip components;

off-chip components; and

interface components connecting the on-chip components and the off-chip components to form a magnetic shielding loop, wherein the magnetic shielding loop magnetically isolates at least one of input terminals and noise-generating elements of the circuit.

2. A structure minimizing magnetic coupling associated with a circuit on an integrated circuit (IC), the structure comprising:

a first conductive path formed in a die of the IC;

a second conductive path formed in a package of the IC;

conductive interface components to connect the first and second conductive paths and form a magnetic shielding loop, wherein the magnetic shielding loop magnetically isolates at least one of input terminals and noise-generating elements of the circuit.

3. The structure of claim 2 , wherein the conductive interface components include:

chip contacts connected to the first conductive path;

package contacts connected to the second conductive path; and

bonding wires connecting the chip contacts and the package contacts.

4. A structure minimizing magnetic coupling associated with a circuit on an integrated circuit (IC), the structure comprising:

a first conductive path formed in a die of the IC;

second conductive paths formed in a package housing the IC;

a third conductive path formed in a printed circuit board for mounting the IC; and

conductive interface components to connect the first, second, and third conductive paths and form a magnetic shielding loop, wherein the magnetic shielding loop magnetically isolates at least one of input terminals and noise-generating elements of the circuit.

5. The structure of claim 4 , wherein the conductive interface components include:

chip contacts connected to the first conductive path;

package contacts connected to the second conductive path;

bonding wires connecting the chip contacts and the package contacts;

package solder bumps/contacts connected to the third conductive path; and

conductors connecting the package contacts and the package solder bumps/contacts.

6. A structure minimizing magnetic coupling associated with a circuit on an integrated circuit (IC), the structure comprising:

first conductive components in a first substrate;

second conductive components in a second substrate; and

third conductive components for connecting the first and second conductive components to create a magnetic shielding loop for at least one of input terminals and noise-generating elements of the circuit.

7. The structure of claim 6 , further including:

fourth conductive components in a third substrate; and

fifth conductive components for connecting the second and fourth conductive components.

8. A method of minimizing magnetic coupling associated with a circuit on an integrated circuit (IC), the method comprising:

creating a magnetic shielding loop spanning a plurality of substrates, wherein the plurality of substrates include at least a die substrate and a package substrate.

9. The method of claim 8 , wherein the plurality of substrates include the die substrate, the package substrate, and a printed circuit board substrate.

Assignments (3)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 20, 2012
From: QUALCOMM ATHEROS, INC.
To: QUALCOMM INCORPORATED
Reel/Frame 029328/0052 →
MERGER Recorded Jul 15, 2011
From: ATHEROS COMMUNICATIONS, INC.
To: QUALCOMM ATHEROS, INC.
Reel/Frame 026599/0360 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 25, 2006
From: TERROVITIS, MANOLIS
To: ATHEROS COMMUNICATIONS, INC.
Reel/Frame 017679/0303 →