Enhancement-depletion Darlington device
View Patent ↗An apparatus comprising a Darlington transistor pair comprising a first transistor and a second transistor. The first transistor may have a gate configured to receive an input signal. The second transistor may have a gate coupled to a source of the first transistor. The Darlington transistor pair may be configured to generate an output signal at a drain of the first transistor and a drain of the second transistor in response to the input signal. The first transistor may be implemented as an enhancement mode device and the second transistor may be implemented as a depletion mode device.
1. An apparatus comprising:
a Darlington transistor pair comprising (a) a first transistor having a gate configured to receive an input signal, (b) a second transistor having a gate coupled to a source of said first transistor and (c) an inductor element coupled to said source of said first transistor, wherein (i) said Darlington transistor pair is configured to generate an output signal at a drain of said first transistor and a drain of said second transistor in response to said input signal and (ii) said first transistor comprises an enhancement mode device and said second transistor comprises a depletion mode device.
2. The apparatus according to claim 1 , further comprising:
a second inductor element coupled to said source of said second transistor.
3. The apparatus according to claim 2 , wherein the second inductor is coupled to a first inductor element to provide a broadband voltage divider for adjusting the RF signal being applied to the second transistor.
4. The apparatus according to claim 1 , further comprising:
a bias circuit coupled to said first transistor.
5. The apparatus according to claim 1 , further comprising:
a bias circuit coupled to said second transistor.
6. The apparatus according to claim 1 , wherein (i) said first transistor comprises (i) a depletion mode transistor and (ii) said second transistor comprises an enhancement mode transistor.
7. The apparatus according to claim 6 , wherein said apparatus is directly coupled to an external circuit through said gate of said first transistor, wherein said gate has a substantially 0V DC bias.
8. The apparatus according to claim 6 , wherein said apparatus is configured to be an external Integrated Circuit (IC).
9. The apparatus according to claim 1 , wherein first and second transistors are manufactured using a processing technology selected from the group consisting of GaN, SiC, PHEMT and other semiconductor device technologies.
10. The apparatus according to claim 1 , wherein (i) said first transistor is AC coupled to said second transistor through a first capacitor and (ii) a first inductor is coupled between the source of the first transistor and ground.
11. The apparatus according to claim 1 , wherein said apparatus minimizes a knee voltage of said Darlington transistor pair.
12. The apparatus according to claim 1 , wherein said apparatus is configured to provide a linear output.
13. The apparatus according to claim 1 , wherein said apparatus operates like a single transistor device.
14. The apparatus according to claim 1 , wherein said apparatus provides a knee voltage similar to a single transistor common-source device.
15. The apparatus according to claim 1 , further comprising:
a spiral inductor connected to said source of said first transistor to provide a high RF impedance and a low DC impedance.
16. An apparatus comprising:
a Darlington transistor pair comprising a first transistor having a gate configured to receive an input signal and a second transistor having a gate coupled to a source of said first transistor, wherein (i) said Darlington transistor pair is configured to generate an output signal at a drain of said first transistor and a drain of said second transistor in response to said input signal, (ii) said first transistor comprises an enhancement mode device and said second transistor comprises a depletion mode device, (iii) said first transistor is AC coupled to said second transistor through a first capacitor and (iv) a first inductor is coupled between the source of the first transistor and ground.
17. The apparatus according to claim 16 , wherein (i) said first transistor comprises (i) a depletion mode transistor and (ii) said second transistor comprises an enhancement mode transistor.
18. An apparatus comprising:
a Darlington transistor pair comprising (a) a first transistor having a gate configured to receive an input signal, (b) a second transistor having a gate coupled to a source of said first transistor and (c) a spiral inductor connected to said source of said first transistor to provide a high RF impedance and a low DC impedance, wherein (i) said Darlington transistor pair is configured to generate an output signal at a drain of said first transistor and a drain of said second transistor in response to said input signal and (ii) said first transistor comprises an enhancement mode device and said second transistor comprises a depletion mode device.
19. The apparatus according to claim 18 , wherein (i) said first transistor comprises (i) a depletion mode transistor and (ii) said second transistor comprises an enhancement mode transistor.