LOG-BASED ROLLBACK-RECOVERY
Log-Based Rollback Recovery for system failures. The system includes a storage medium, and a component configured to transition through a series of states. The component is further configured to record in the storage medium the state of the component every time the component communicates with another component in the system, the system being configured to recover the most recent state recorded in the storage medium following a failure of the component.
1 . A system, comprising:
a storage medium;
a component configured to transition through a series of states, and record in the storage medium the state of the component every time the component communicates with another component in the system; and
recovery manager configured to recover the most recent state of the component recorded in the storage medium following a failure of the component.
2 . The system of claim 1 wherein the component is further configured to perform a process having multiple threads, the process resulting in the component transitioning through the series of states.
3 . The system of claim 2 wherein at least two of the threads share a common state as the component transitions through the series of states.
4 . The system of claim 3 wherein the common state comprises an access by said at least two of the threads to a common resource.
5 . The system of claim 1 wherein the component is further configured to perform multiple processes in parallel, the processes resulting in the component transitioning through the series of states.
6 . The system of claim 5 wherein at least one of the processes comprises multiple threads.
7 . The system of claim 5 wherein at least two of the processes share a common state as the component transitions through the series of states.
8 . The system of claim 7 wherein the common state comprises an access by said at least two of the processes to a common resource.
9 . Computer-readable media containing a set of program instructions executable by hardware in a component of a system while the component is transitioning through a series of states, comprising:
a routine to record in a storage medium the state of the component every time the component communicates with another component in the system.
10 . The computer-readable media of claim 9 wherein the component is further configured to execute multiple threads, the execution of the multiple threads resulting in the component transitioning through the series of states.
11 . The computer-readable media of claim 10 wherein at least two of the threads share a common state as the component transitions through the series of states.
12 . The computer-readable media of claim 11 wherein the common state comprises an access by said at least two of the threads to a common resource.
13 . The computer-readable media of claim 9 wherein the component is further configured to perform multiple processes in parallel, the processes resulting in the component transitioning through the series of states.
14 . The computer-readable media of claim 13 wherein at least one of the processes comprises multiple threads.
15 . The computer-readable media of claim 14 wherein at least two of the processes share a common state as the component transitions through the series of states.
16 . The computer-readable media of claim 15 wherein the common state comprises an access by said at least two of the processes to a common resource.
17 . The computer-readable media of claim 9 wherein the set of program instructions comprises a checkpoint library accessible to an application running on the hardware, the running of the application resulting in the component transitioning through the series of states.
18 . The computer-readable media of claim 17 wherein the hardware supports an operating system, and wherein communications between the application and the operating system flow through the checkpoint library.
19 . A method of checkpointing a component in a system while the component is transitioning through a series of states, the method comprising;
recording in a storage medium the state of the component every time the component communicates with another component in the system; and
recovering the most recent state recorded in the storage medium following a failure of the component.
20 . The method of claim 19 wherein the component is performing a process having multiple threads, the process resulting in the component transitioning through the series of states.
21 . The method of claim 20 wherein at least two of the threads share a common state as the component transitions through the series of states.
22 . The method of claim 21 wherein the common state comprises accessing a common resource by said at least two of the threads.
23 . The method of claim 19 wherein the component is performing multiple processes in parallel, the processes resulting in the component transitioning through the series of states.
24 . The method of claim 23 wherein at least two of the processes sharing a common state as the component transitions through the series of states.
25 . The method of claim 24 wherein the common state comprises accessing a common resource by said at least two of the processes.
26 . A component configured to operate in a system, comprising:
means for transitioning through a series of states; and
means for recording in a storage medium the state of the component every time the component communicates with another component in the system.
27 . The component of claim 26 wherein the means for transitioning through a series of states comprises a process having multiple threads.
28 . The component of claim 27 wherein at least two of the threads share a common state.
29 . The component of claim 28 wherein the common state comprises an access by said at least two of the threads to a common resource.
30 . The component of claim 26 wherein the means for transitioning through a series of states comprises multiple processes performed in parallel.
31 . The component of claim 30 wherein at least one of the processes comprises multiple threads.
32 . The component of claim 30 wherein at least two of the processes share a common state as the component transitions through the series of states.
33 . The system of claim 32 wherein the common state comprises an access by said at least two of the processes to a common resource.
34 . A processing node configured to operate in a system, comprising:
a processor configured to transition through a series of states, the processor having a checkpoint library configured to record in a storage medium the state of the processor every time the processor communicates with another component of the system.
35 . The processing node of claim 34 wherein the processor is further configured to perform a process having multiple threads, the process resulting in the processor transitioning through the series of states.
36 . The processing node of claim 35 wherein at least two of the threads share a common state as the processor transitions through the series of states.
37 . The processing node of claim 36 wherein the common state comprises an access by said at least two of the threads to a common resource.
38 . The processing node of claim 34 further comprising a second processor configured to transition through a series of states, the second processor having a second checkpoint library configured to record in the storage medium the state of the processing node every time the second processor communicates with another component of the system
39 . The processing node of claim 38 wherein the processors are configured to perform multiple processes in parallel, the processes resulting in the processors transitioning through the series of states.
40 . The processing node of claim 39 wherein at least one of the processes comprises multiple threads.
41 . The processing node of claim 39 wherein at least two of the processes share a common state as the component transitions through the series of states.
42 . The processing node of claim 41 wherein the common state comprises an access by said at least two of the processes to a common resource.
43 . The processing node of claim 34 wherein the processor includes an application that causes the processor to transition through the series of states, the checkpoint library being accessible to the application.
44 . The processing node of claim 43 wherein the processor further includes an operating system, and wherein communications between the application and the operating system flow through the checkpoint library.