Low contact resistance CMOS circuits and methods for their fabrication
View Patent ↗A low contact resistance CMOS integrated circuit and method for its fabrication are provided. The CMOS integrated circuit comprises a first transition metal electrically coupled to the N-type circuit regions and a second transition metal different than the first transition metal electrically coupled to the P-type circuit regions. A conductive barrier layer overlies each of the first transition metal and the second transition metal and a plug metal overlies the conductive barrier layer.
1. A method for fabricating a CMOS integrated circuit having an N-type drain region and a P-type drain region, the method comprising the steps of:
depositing a high barrier height silicide forming metal in contact with the P-type drain region;
heating the high barrier height silicide forming metal to form a high barrier height metal silicide in contact with the P-type drain region;
depositing a low barrier height silicide forming metal in contact with the N-type drain region;
heating the low barrier height silicide forming metal to form a low barrier height metal silicide in contact with the N-type drain region;
depositing and patterning a dielectric layer to form a first opening exposing a portion of the high barrier height metal silicide and a second opening exposing a portion of the low barrier height metal silicide;
depositing a low barrier height metal into the second opening and contacting the portion of the low barrier height metal silicide;
depositing a high barrier height metal into the first opening and contacting the portion of the high barrier height metal silicide;
depositing a conductive capping layer in contact with the high barrier height metal and in contact with the low barrier height metal; and
filling the first opening and the second opening with a plug metal in contact with the conductive capping layer.
2. The method of claim 1 wherein the step of depositing a high barrier height metal comprises the step of depositing a metal selected from the group consisting of platinum, palladium, gold, silver, aluminum and alloys thereof.
3. The method of claim 2 wherein the step of depositing a low barrier height metal comprises the step of depositing a metal selected from the group consisting of scandium and magnesium.
4. The method of claim 3 wherein the step of depositing a conductive capping layer comprises the step of depositing a layer of material selected from the group consisting of titanium nitride and tantalum nitride.
5. The method of claim 4 wherein the step of filling comprises the step of filling the first opening and the second opening with a metal from the group consisting of copper and tungsten.