Amplitude regulated crystal oscillator
View Patent ↗To maintain the amplitude of an oscillating signal within a defined range, the detected peak level of the oscillating signal is compared to a reference voltage. If the detected peak level is determined as being greater than the reference voltage, the common source/drain voltage of a differential amplifier driving the crystal oscillator across its input terminals is reduced so as to lower the amplitude of the oscillation signal. If the detected peak level is determined as being smaller than the reference voltage, the common source/drain voltage of the differential amplifier driving the crystal oscillator is increase so as to raise the amplitude of the oscillation signal.
1. A circuit comprising:
a peak detector adapted to detect a peak level of an oscillating signal;
a regulator adapted to define an upper limit of an amplitude of the oscillating signal in response to a first signal; and
an oscillator having a pair of output terminals configured to drive a crystal oscillator external to the circuit, wherein an output terminal of the oscillator generates the oscillating signal, wherein said regulator further comprises first and second transistors disposed in a first leg and adapted to establish a DC bias point of the first signal, wherein said first and second transistors are diode-connected transistors; and
a comparator adapted to a generate a rail-to-rail voltage signal in response to the oscillating signal.
2. The circuit of claim 1 wherein said regulator further comprises:
third and fourth diode-connected transistors disposed in a second leg and adapted to generate a reference voltage signal.
3. The circuit of claim 2 wherein said regulator further comprises:
a differential amplifier adapted to receive at its first terminal a second voltage signal generated by shifting the voltage level of the reference voltage signal, and a second terminal adapted to receive the detected peak level voltage, said differential amplifier adapted to vary the voltage level of the first signal in response.
4. The circuit of claim 3 wherein said regulator further comprises:
a fifth transistor having a gate terminal adapted to receive the reference voltage and a drain terminal adapted to supply the level shifted reference voltage; and
a sixth transistor adapted to receive the level-shifted reference voltage at its drain terminal; said sixth transistor receiving a gate voltage supplied by a second reference voltage.
5. The circuit of claim 4 wherein said peak detector further comprises:
a seventh transistor having a gate terminal adapted to receive the oscillating signal, and a source terminal adapted to supply the detected peak voltage level;
an eighth transistor adapted to receive the detected peak voltage level at its drain terminal, and a gate terminal adapted to receive the second reference voltage.
6. The circuit of claim 5 wherein the seventh transistor matches the fifth transistor and the eight transistor matches the sixth transistor.
7. The circuit of claim 6 wherein said oscillator further comprises:
a ninth transistor having a gate terminal adapted to receive the first voltage signal, and
a tenth transistor having a gate terminal coupled to a first terminal of the crystal oscillator and a source terminal coupled to the source terminal of the ninth transistor; wherein a drain terminal of the tenth transistor is coupled to a second terminal of the crystal oscillator.
8. The circuit of claim 7 further comprising:
a biasing circuit configured to supply the second reference voltage and further configured to power down the circuit.
9. A method of regulating an amplitude of an oscillating signal, the method comprising:
detecting a peak level of the oscillating signal;
defining an upper limit of an amplitude of the oscillating signal in response to a first signal;
comparing the detected peak level with the defined upper amplitude level to vary a voltage level of the first signal in response; and
maintaining the amplitude of the oscillating signal in accordance with the voltage level of the first signal
establishing a DC bias voltage of the first signal using first and second transistors disposed in a first leg, wherein said first and second transistors are diode-connected transistors.
10. The method of claim 9 further comprising:
generating a rail-to-rail voltage signal in response to the oscillating signal.
11. The method of claim 9 further comprising:
generating a reference voltage signal.
12. The method of claim 11 further comprising:
shifting the voltage level of the reference signal; and
amplifying a difference between the level-shifted reference voltage and the detected peak level of the oscillating signal; and
varying the voltage level of the first signal in response the amplification.