Methods, Systems, and Computer Program Products for Providing Access to Addressable Entities Using a Non-Sequential Virtual Address Space

1 . A method for providing access to addressable entities using a non-sequential virtual address space, the method comprising:

assigning an identifier from a non-sequential address space to an addressable entity;

associating the identifier corresponding to the addressable entity with a first memory location for storing the corresponding addressable entity; and

using the identifier corresponding to the addressable entity in a first machine code instruction to access the addressable entity from the first memory location for processing the first machine code instruction by a processor.

2 . The method of claim 1 comprising storing an association of the identifier corresponding to the addressable entity with the first memory location in a memory management system (MMS).

3 . The method of claim 2 wherein the memory management system includes at least one of a page table, a map table, and a TLB for enabling the mapping of a virtual address compatible with the MMS within the memory management system to a physical address.

4 . The method of claim 1 wherein the first memory location includes at least one of a random access memory (RAM) location, a read-only memory (ROM) location, and a location in a persistent memory medium.

5 . The method of claim 1 comprising storing the addressable entity to a second memory location and associating the identifier corresponding to the addressable entity with the second memory location in association with the storing of the corresponding addressable entity to the second memory location.

6 . The method of claim 1 wherein the addressable entity includes one of an executable program function, a program object having an executable component, a virtual register, a parameter, a data variable, and a data constant.

7 . The method of claim 1 wherein the first memory location includes a RAM location and wherein the method further comprises, in response to completion of processing the first machine code instruction using the identifier of the addressable entity by the processor, preserving the association of the identifier corresponding to the addressable entity and using the identifier corresponding to the addressable entity to access the addressable entity within the RAM location during a subsequent processing by the processor of a second machine code instruction using the identifier of the addressable entity.

8 . The method of claim 1 wherein the first memory location includes a first RAM location and wherein the method further comprises, in response to completion of processing by the processor of the first machine code instruction using the identifier of the addressable entity, storing the addressable entity in a persistent memory location, mapping the addressable entity into a second RAM location and using the identifier corresponding to the addressable entity to access the addressable entity within the second RAM location during a subsequent processing by the processor of a second machine code instruction using the identifier of the addressable entity.

9 . The method of claim 1 wherein the identifier corresponding to the addressable entity is associated with a symbol usable within a programming syntax to allow the association of the identifier corresponding to the addressable entity with the first memory location to be resolved at a machine code instruction level within a microprocessor.

10 . The method of claim 1 comprising storing an association of a portion of the identifier corresponding to the addressable entity with a portion of the first memory location in a TLB and wherein using the identifier corresponding to the addressable entity to access the addressable entity during processing of the first machine code instruction includes locating in the TLB, using the portion of the identifier, a portion of a physical address of the first memory location.

11 . The method of claim 1 comprising storing an association of a portion of the identifier corresponding to the addressable entity with the first memory location in a memory management system page table and wherein using the identifier corresponding to the addressable entity to access the addressable entity space during processing of the first machine code instruction includes searching the memory management system page table using the portion of the identifier and calculating a physical address of the first memory location in response to identification of the association of the portion of the identifier corresponding to the addressable entity with the first memory location in the memory management system page table.

12 . The method of claim 1 wherein the first memory location comprises a persistent memory location and comprising storing an association of a portion of the identifier corresponding to the addressable entity with the persistent memory location in a map table and wherein using the identifier corresponding to the addressable entity to access the addressable entity during processing of the first machine code instruction includes searching the map table using the portion of the identifier and calculating a physical address of the persistent memory location in response to identification of the association of the portion of the identifier corresponding to the addressable entity with the persistent memory location in the map table.

13 . The method of claim 1 wherein the addressable entity includes a code block and wherein the identifier is used to jump to the code block during processing of the first machine code instruction.

14 . The method of claim 1 wherein the addressable entity includes a data variable and wherein the method further comprises at least one of storing a value in and reading a value from the first memory location using the identifier during processing of the first machine code instruction.

15 . The method of claim 1 comprising storing the addressable entities associated with the active non-sequential virtual address space to persistent memory.

16 . The method of claim 15 comprising retrieving at least a portion of the addressable entities from persistent memory.

17 . The method of claim 1 wherein the non-sequential virtual address space co-exists with a sequential virtual address space.

18 . The method of claim 17 wherein the first machine code instruction is accessed by the processor from within one of the sequential virtual address space and the non-sequential virtual address space.

19 . The method of claim 1 wherein the addressable entity includes one of an executable addressable entity and a non-executable addressable entity.

20 . The method of claim 1 wherein processing the first machine-code instruction using the identifier corresponding to the addressable entity to access the addressable entity from the first memory location includes determining whether the identifier is an MMS address.

21 . The method of claim 20 wherein, in response to determining that the identifier is an MMS address, locating the addressable entity in the first memory location using at least one of a translation lookaside buffer (TLB), a page table, and a map table.

22 . The method of claim 20 wherein, in response to determining that the identifier is not an MMS address, locating the first memory location using at least one of a TLB and a page table.

23 . The method of claim 1 wherein using the identifier corresponding to the addressable entity to access the addressable entity from the first memory location during processing of the first machine code instruction includes processing the identifier within the processor by indexing a TLB with the identifier to locate the addressable entity within memory.

24 . A system for providing access to addressable entities in a non-sequential virtual address space, the system comprising:

an MMS configured for assigning an identifier from a non-sequential address space to an addressable entity and associating the identifier corresponding to the addressable entity with a first memory location for storing the corresponding addressable entity; and

a processor configured for using the identifier corresponding to the addressable entity to access the addressable entity from the first memory location during processing of a machine code instruction.

25 . A system for providing access to addressable entities in a non-sequential virtual address space, the system comprising:

a memory management system (MMS) for managing a non-sequential virtual address space; and

a processor including:

an instruction set processor (ISP) for processing a first machine code instruction that includes an identifier as an operand, where the identifier is from the non-sequential virtual address space and references an index of a location managed by the MMS for storing, at the index referenced by the identifier, an association between an addressable entity and a first memory location for storing the addressable entity; and

a memory management unit (MMU) enabled to locate the first memory location associated with the addressable entity stored at the location indexed by the identifier within the MMS to allow the processor to access the addressable entity in the first memory location during the processing of the machine code instruction by the ISP.

26 . The system of claim 25 wherein the MMS includes at least one of a page table, a map table, and a translation lookaside buffer (TLB).

27 . The system of claim 25 wherein the processor is adapted to process a second machine code instruction for storing the addressable entity to a second memory location and wherein the MMS is adapted to associate the identifier corresponding to the addressable entity with the second memory location for storing the corresponding addressable entity.

28 . The system of claim 25 wherein the addressable entity is one of an executable program function, a program object having an executable component, a virtual register, a parameter, a data variable, and a data constant.

29 . The system of claim 25 wherein the first memory location includes a first RAM location and wherein the processor is adapted to, in response to completion of processing of the first machine code instruction, store the addressable entity in a persistent memory location, to copy the addressable entity into a second RAM location, to associate the identifier with the second RAM location, and to use the identifier corresponding to the addressable entity to query the MMS for the second RAM location to access the addressable entity within the second RAM location during a subsequent processing of a second machine code instruction by the processor.

30 . The system of claim 25 wherein the first memory location includes at least one of a RAM location and a memory location in a persistent memory medium.

31 . The system of claim 25 wherein the identifier corresponding to the addressable entity is associated with a symbol usable within a programming syntax and wherein the MMS is adapted to use the symbol to resolve the association of the identifier corresponding to the addressable entity with the first memory location and wherein the processor is adapted to access the addressable entity at an instruction level by querying the MMS for the first memory location.

32 . The system of claim 25 wherein the MMS includes at least one of a TLB, a page table, and a map table and wherein the processor is adapted to use the identifier corresponding to the addressable entity to query the at least one of the TLB, the page table, and the map table to identify a physical address of the first memory location to access the addressable entity during processing of the first machine code instruction.

33 . The system of claim 25 wherein the MMS includes a map table and wherein the processor is adapted to use the identifier corresponding to the addressable entity to query the map table and wherein the processor is further adapted to calculate a physical address of the first memory location in response to identification of the association of the identifier corresponding to the addressable entity with the first memory location in the map table.

34 . The system of claim 25 wherein the addressable entity includes a code block and wherein the processor is adapted to use the identifier to query the MMS for the first memory location and to jump to the code block during processing of the first machine code instruction.

35 . The system of claim 25 wherein the addressable entity includes a data variable and wherein the processor is adapted to use the identifier to query the MMS for the first memory location and to perform at least one of storing a value in and retrieving a value from the first memory location during processing of the first machine code instruction.

36 . The system of claim 25 wherein the processor is adapted to operate within the virtual address space and wherein the processor is further adapted to perform an operation including at least one of storing the addressable entities associated with an portion of the virtual address space to a persistent memory and retrieving the portion of the addressable entities associated with the active portion of the virtual address space from the persistent memory.

37 . The system of claim 25 wherein the memory associated with the non-sequential virtual address space is a structured memory.

38 . The system of claim 25 wherein the non-sequential virtual address space coexists with a sequential address space and wherein the processor is adapted to process identifiers from both the non-sequential virtual address space and the sequential virtual address space.

39 . The system of claim 38 wherein the processor is adapted to execute an executable system resource associated with an identifier within one of the sequential virtual address space and the non-sequential virtual address space.

40 . The system of claim 25 wherein the addressable entity includes one of an executable addressable entity and a non-executable addressable entity.

41 . The system of claim 25 wherein the processor is adapted to use the identifier corresponding to the addressable entity to query the MMS for the first memory location to access the addressable entity from the first memory location during processing of the first machine code instruction.

42 . The system of claim 25 wherein the MMS includes at least one of a TLB, a page table, and a map table and wherein the processor is adapted to use the identifier corresponding to the addressable entity to query the at least one of a TLB, a page table, and a map table for the first memory location to access the addressable entity from the first memory location during processing of the first machine code instruction.

43 . A system for providing access to addressable entities in a non-sequential virtual address space, the system comprising:

means for assigning an identifier from a non-sequential address space to an addressable entity;

means for associating the identifier corresponding to the addressable entity with a first memory location for storing the corresponding addressable entity; and

means for using the identifier corresponding to the addressable entity to access the addressable entity from the first memory location during processing of a machine code instruction.

44 . A computer program product comprising computer-executable instructions embodied in a computer-readable medium for performing steps comprising:

assigning an identifier from a non-sequential virtual address space to an addressable entity;

associating the identifier corresponding to the addressable entity with a first memory location for storing the corresponding addressable entity; and

using the identifier corresponding to the addressable entity to access the addressable entity from the first memory location during processing of a machine code instruction.