System for selectively synchronizing high-assurance software tasks on multiple processors at a software routine level

1. A task matching circuit for synchronizing software on a plurality of processors, the task matching circuit comprising:

a first input from a first processor configured to receive a first software routine identifier, wherein one value of the first software routine identifier uniquely identifies, based on the one value of the first software routine identifier, a first routine to be executed by the first processor, the first routine being one of a plurality of routines and comprising a predetermined plurality of software instructions;

a second input from a second processor configured to receive a plurality of second software routine identifiers from a queue of second software routine identifiers, wherein:

each of the plurality of second software routine identifiers uniquely identifies a corresponding one of a plurality of second routines to be executed by the second processor, and

each of the second routines is one of the plurality of routines and comprises a predetermined plurality of software instructions;

an analysis sub-circuit, at least partially embodied in hardware, configured to compare the first software routine identifier with each of the plurality of second software routine identifiers and determine if the first software routine identifier and a presently compared one of the second software routine identifiers correspond to a same routine; and

an output coupled to at least one of the first or second processors, wherein:

the output indicates when the first software routine identifier and one of the plurality of second software routine identifiers do not correspond to the same routine, and

the analysis sub-circuit is configured to delay the first processor, and select each of the plurality of second software routine identifiers in the queue of second software routine identifiers, without the second processor executing a second routine corresponding to a presently selected second software routine identifier, until the first software routine identifier and the presently selected second software routine identifier correspond to the same routine.

2. The task matching circuit for synchronizing software on the plurality of processors as recited in claim 1 , wherein the analysis sub-circuit is configured to cause the first processor to perform more software routines than the second processor during normal operation.

3. The task matching circuit for synchronizing software on the plurality of processors as recited in claim 1 , wherein the analysis sub-circuit is configured to receive an initiation message from the first processor, and initiate a task check process to synchronize the first and second processors in executing the first routine.

4. The task matching circuit for synchronizing software on the plurality of processors as recited in claim 1 , wherein the output indicates that the first software routine identifier and the presently selected second software routine identifier correspond to the same routine only when the second software routine produces a result that the first software routine also produces.

5. The task matching circuit for synchronizing software on the plurality of processors as recited in claim 1 , wherein the analysis sub-circuit is configured to delay at least one of the first and second processors from executing a software routine corresponding to one of the first software routine identifier and the presently selected second software routine identifier until the output indicates that the first and second software routine identifiers correspond to the same routine.

6. The task matching circuit for synchronizing software on the plurality of processors as recited in claim 1 , further comprising the first processor and the second processor wherein the first processor operates off a first clock signal different from a second clock signal of the second processor.

7. The task matching circuit for synchronizing software on the plurality of processors as recited in claim 1 , wherein the first processor cannot communicate directly with the second processor.

8. The task matching circuit for synchronizing software on the plurality of processors as recited in claim 1 , wherein the first software routine identifier is created from contents of the first routine.

9. The task matching circuit for synchronizing software on the plurality of processors as recited in claim 1 , wherein the first processor is a different design from the second processor.

10. The task matching circuit for synchronizing software on the plurality of processors as recited in claim 1 , wherein the first processor and the second processor execute the same routine, at least partially simultaneously in time.

11. The task matching circuit for synchronizing software on the plurality of processors as recited in claim 1 , wherein the analysis sub-circuit is configured to determine, for a subset of a plurality of software routine identifiers, that the first software routine identifier and the presently selected second software routine identifiers correspond, and the analysis sub-circuit does not delay the first processor unless at least one of the first software routine identifier and the presently selected second software routine identifier is one of the subset.

12. A high-assurance circuit for coordinating performance on a plurality of sub-circuits, the high-assurance circuit comprising:

a first input from a first sub-circuit configured to receive a first operation identifier, wherein one value of the first operation identifier uniquely identifies, based on the one value of the first operation identifier, a first software operation comprising a predetermined plurality of software instructions to be executed by the first sub-circuit, the first software operation being one of a plurality of software operations;

a second input from a second sub-circuit configured to receive a plurality of second operation identifiers from a queue of second operation identifiers, wherein:

each of the plurality of second operation identifiers uniquely identifies a corresponding one of a plurality of second software operations to be executed by the second sub-circuit, and

each of the second software operations comprises a predetermined plurality of software instructions;

an analysis sub-circuit, at least partially embodied in hardware, configured to compare the first operation identifier with each of the plurality of second operation identifiers and determine if the first operation identifier corresponds with a presently compared one of the second operation identifiers; and

an output coupled to at least one of the first or second sub-circuits, wherein:

the output indicates when the first operation identifier and one of the plurality of second operation identifiers do not correspond to functionally overlapping software operations, and

the analysis sub-circuit is configured to delay the first sub-circuit, and select each of the plurality of second operation identifiers in the queue of second operation identifiers, without the second sub-circuit executing a second software operation corresponding to a presently selected second operation identifier, until the first operation identifier and the presently selected second operation identifier correspond to functionally overlapping software operations.

13. The high-assurance circuit for coordinating performance on the plurality of sub-circuits as recited in claim 12 , wherein the analysis sub-circuit is configured to cause the first sub-circuit to perform more functions than the second sub-circuit during normal operation.

14. The high-assurance circuit for coordinating performance on the plurality of sub-circuits as recited in claim 12 , further comprising the first sub-circuit wherein the first sub-circuit is integral to a processor.

15. The high-assurance circuit for coordinating performance on the plurality of sub-circuits as recited in claim 14 , further comprising the second sub-circuit wherein the second sub-circuit comprises a processor.

16. The high-assurance circuit for coordinating performance on the plurality of sub-circuits as recited in claim 15 , wherein the first sub-circuit operates off a first clock signal different from a second clock signal of the second sub-circuit.

17. The high-assurance circuit for coordinating performance on the plurality of sub-circuits as recited in claim 12 , wherein functionally overlapping operations produce at least one result in common when given a same set of inputs corresponding to the at least one result.

18. The high-assurance circuit for coordinating performance on the plurality of sub-circuits as recited in claim 12 , wherein the analysis sub-circuit is configured to delay at least one of the first and second sub-circuits from executing a software operation corresponding to the first operation identifier and the presently selected second operation identifier until the output indicates that the first operation identifier and the presently selected second operation identifier correspond.

19. The high-assurance circuit for coordinating performance on the plurality of sub-circuits as recited in claim 12 , wherein the analysis sub-circuit is configured to determine, for a subset of a plurality of operation identifiers, that the first and second operation identifiers correspond, and the analysis sub-circuit does not delay the first sub-circuit unless at least one of the first operation identifier and the presently selected second operation identifier is one of the subset.