IP Library Granted Patent US 7,423,644
Granted Patent B2
US 7,423,644 · App. 11/428,756 · Granted Sep 9, 2008

Method and apparatus for dual pass adaptive tessellation

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Quick Facts
Patent No.
US 7,423,644
App. No.
11/428,756
Granted
Sep 9, 2008
Kind
B2
Abstract

A method and apparatus for dual pass adaptive tessellation includes a vertex grouper tessellator operably coupled to receive primitive information and an index list and a shader processing unit coupled to the vertex grouper tessellator. During a first pass, the shader processing unit receives primitive indices generated from the primitive information and an auto-index value for each of the plurality of primitive indices. The method and apparatus further includes a plurality of vertex shader input staging registers operably coupled to the shader sequence, wherein the plurality of vertex shader input staging registers are coupled to a plurality of vertex shaders such that in response to a shader sequence output, the vertex shaders generate tessellation factors. The tessellation factors are provided to the vertex grouper tessellator such that the vertex grouper tessellator generates a per-process vector output, a per primitive output and a per packet output during a second pass.

Claims (12)

1. An apparatus for dual pass adaptive tessellation comprising:

a vertex grouper tessellator operatively coupled to a plurality of vertex shaders wherein, during a first pass:

the vertex grouper tessellator is operative to generate primitive indices and corresponding auto-index values based on primitive information and an index list; and

the plurality of vertex shaders are operative to generate tessellation factors based on the primitive indices and the corresponding auto-index values.

2. The apparatus of claim 1 , wherein during the first pass the vertex grouper tessellator is further operative to generate at least one of: a per process vector output, a per primitive output and a per packet output.

3. The apparatus of claim 1 , further comprising:

a shader processing unit such that during the first pass the shader processing unit is operative to generate a shader sequence output based on the primitive indices and the corresponding auto-index values; and

wherein the plurality of vertex shaders are operative to generate tessellation factors based on the shader sequence output.

4. The apparatus of claim 1 , wherein, during a second pass:

the vertex grouper tessellator, based on the plurality of tessellation factors, is operative to generate coordinates for at least one surface and an auto-index value for each of the plurality of tessellation factors; and

the plurality of vertex shaders are operative to generate tessellation vertices for the at least one surface based at least on the generated coordinates and the auto-index values corresponding to the plurality of tessellation factors.

5. The apparatus of claim 4 , wherein the plurality of vertex shaders are operative to fetch control points specified by the auto-index values corresponding to the plurality of tessellation factors, and wherein the tessellation vertices are generated based on the generated coordinates and the control points.

Assignments (2)
CHANGE OF NAME Recorded May 12, 2011
From: ATI TECHNOLOGIES INC.
To: ATI TECHNOLOGIES ULC
Reel/Frame 026270/0027 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 5, 2006
From: GOEL, VINEET; MOREIN, STEPHEN L.; HARTOG, ROBERT SCOTT
To: ATI TECHNOLOGIES INC.
Reel/Frame 017879/0272 →