Level shifter and a display device having the same

1. A level shifter, comprising:

a first transistor including a gate electrode receiving a first driving voltage, and a source electrode receiving an input signal through an input terminal;

a second transistor including a source electrode receiving the first driving voltage, and a drain electrode electrically connected to a drain electrode of the first transistor through a first node;

a third transistor including a source electrode receiving a second driving voltage, a drain electrode electrically connected to a gate electrode of the second transistor through a second node, and a gate electrode receiving the input signal;

a fourth transistor including a source electrode receiving the first driving voltage, a gate electrode electrically connected to the drain electrode of the first transistor through the first node, and a drain electrode electrically connected to the drain electrode of the third transistor through the second node;

a fifth transistor including a source electrode electrically connected to the drain electrode of the second transistor, a gate electrode electrically connected to the first node, and a drain electrode electrically connected to the gate electrode; and

an inverter that inverts a signal outputted from the second node to apply the inverted signal to an output terminal.

2. The level shifter of claim 1 , wherein each of the first and third transistors is an N-channel metal oxide semiconductor (NMOS) transistor, and each of the second and fourth transistors is a P-channel metal oxide semiconductor (PMOS) transistor.

3. The level shifter of claim 1 , wherein the first transistor has a greater channel width than the second transistor.

4. The level shifter of claim 1 , wherein the third transistor has a greater channel width than the fourth transistor.

5. The level shifter of claim 1 , wherein a ratio of a channel width to a channel length of the first transistor is about 10/6, a ratio of a channel width to a channel length of the second transistor is about 5/10, a ratio of a channel width to a channel length of the third transistor is about 50/6 and a ratio of a channel width to a channel length of the fourth transistor is about 10/6.

6. The level shifter of claim 1 , wherein the inverter comprises a complementary metal oxide semiconductor (CMOS) transistor.

7. The level shifter of claim 6 , wherein the CMOS transistor includes a P-channel metal oxide semiconductor (PMOS) portion and an N-channel metal oxide semiconductor (NMOS) portion, wherein a ratio of a channel width to a channel length of the PMOS portion is about 10/6 and a ratio of a channel width to a channel length of the NMOS portion is about 10/7.

8. The level shifter of claim 1 , wherein a ratio of a channel width to a channel length of the fifth transistor is about 5/5.

9. The level shifter of claim 1 , wherein the fifth transistor is a P-channel metal oxide semiconductor (PMOS) transistor.

10. The level shifter of claim 1 , wherein the first driving voltage is about 5V to about 8.5V, and the second driving voltage is a ground potential.

11. The level shifter of claim 1 , wherein the input signal is externally provided.

12. A level shifter, comprising:

a first driving voltage terminal receiving a first driving voltage;

a second driving voltage terminal receiving a second driving voltage;

an input terminal receiving an input signal;

a first transistor including a gate electrode electrically connected to the first driving voltage terminal, and a source electrode electrically connected to the input terminal;

a second transistor including a source electrode receiving the first driving voltage, and a drain electrode electrically connected to a drain electrode of the first transistor through a first node;

a third transistor including a source electrode electrically connected to the second driving voltage terminal, a drain electrode electrically connected to a gate electrode of the second transistor through a second node, and a gate electrode receiving the input signal;

a fourth transistor including a source electrode electrically connected to the first driving voltage terminal, a gate electrode electrically connected to the drain electrode of the first transistor through the first node, and a drain electrode electrically connected to the drain electrode of the third transistor through the second node;

a fifth transistor including a source electrode electrically connected to the drain electrode of the second transistor, a gate electrode electrically connected to the first node, and a drain electrode electrically connected to the gate electrode;

an inverter that inverts a signal outputted from the second node; and

an output terminal through which the inverted signal is outputted.

13. The level shifter of claim 12 , wherein the input signal is externally provided.

14. A display device including a display panel having a pixel part in a pixel region defined by data and gate lines adjacent to each other, a gate driving part applying a gate voltage to the gate line, and a data driving part applying a data voltage to the data line, at least one of the gate and data driving parts including a level shifter receiving a first signal having a first level through a single input terminal, and outputting a second signal having a second level through a single output terminal, the level shifter comprising:

a first transistor including a gate electrode receiving a first driving voltage, and a source electrode receiving the first signal through the single input terminal;

a second transistor including a source electrode receiving the first driving voltage, and a drain electrode electrically connected to a drain electrode of the first transistor through a first node;

a third transistor including a source electrode receiving a second driving voltage, a drain electrode electrically connected to a gate electrode of the second transistor through a second node, and a gate electrode receiving the first signal;

a fourth transistor including a source electrode receiving the first driving voltage, a gate electrode electrically connected to the drain electrode of the first transistor through the first node, and a drain electrode electrically connected to the drain electrode of the third transistor through the second node; and

an inverter that inverts a signal outputted from the second node to apply the inverted signal to the single output terminal, wherein the inverted signal is the second signal,

wherein the data driving part comprises:

a plurality of shift registers that store data signals synchronized with a clock signal based on a horizontal start signal to shift the stored data signals in sequence;

a latch part that latches the shifted data signals; and

a level converting part including more than one of the level shifters, the level shifters elevating a level of the latched data signals based on a first load signal.

15. The display device of claim 14 , wherein the data driving part further comprises:

a digital-to-analog converting part converting the elevated data signals into a plurality of analog signals based on a second load signal; and

a buffer amplifying part amplifying the analog signals to apply a plurality of liquid crystal driving signals to the data lines.

16. The display device of claim 14 , wherein the first level is lower than the second level.

17. The display device of claim 14 , further comprising a fifth transistor including a source electrode electrically connected to the drain electrode of the second transistor, a gate electrode electrically connected to the first node, and a drain electrode electrically connected to the gate electrode.

18. The display device of claim 14 , wherein the first signal is externally provided.

19. A display device including a display panel having a pixel part in a pixel region defined by data and gate lines adjacent to each other, a gate driving part applying a gate voltage to the gate line, and a data driving part applying a data voltage to the data line, at least one of the gate and data driving parts including a level shifter receiving a first signal having a first level through a single input terminal, and outputting a second signal having a second level through a single output terminal, the level shifter comprising:

a first transistor including a gate electrode receiving a first driving voltage, and a source electrode receiving the first signal through the single input terminal;

a second transistor including a source electrode receiving the first driving voltage, and a drain electrode electrically connected to a drain electrode of the first transistor through a first node;

a third transistor including a source electrode receiving a second driving voltage, a drain electrode electrically connected to a gate electrode of the second transistor through a second node, and a gate electrode receiving the first signal;

a fourth transistor including a source electrode receiving the first driving voltage, a gate electrode electrically connected to the drain electrode of the first transistor through the first node, and a drain electrode electrically connected to the drain electrode of the third transistor through the second node; and

an inverter that inverts a signal outputted from the second node to apply the inverted signal to the single output terminal, wherein the inverted signal is the second signal,

wherein the data driving part comprises:

a level converting part including at least one of the level shifters, the level converting part elevating levels of data signals based on a horizontal start signal;

a plurality of shift registers that stores the elevated data signals synchronized with a clock signal based on the horizontal start signal to shift the stored data signals in sequence; and

a latch part that latches the shifted data signals.

20. The display device of claim 19 , wherein the data driving part further comprises:

a digital-to-analog converting part converting the latched data signals into a plurality of analog signals based on a load signal; and

a buffer amplifying part amplifying the analog signals to apply a plurality of liquid crystal driving signals to the data lines.