Active matrix-type liquid crystal display device
A liquid crystal display device which performs a gradation display for each frame, by eliminating fluctuations in pixel voltage. The device includes a pixel electrode and a MOS transistor circuit driving the pixel electrode. The MOS transistor circuit is disposed near a cross-over point of a scanning line and a signal line, and includes a MOS transistor having a gate electrode connected to the scanning line, and one of a source electrode and a drain electrode connected to the signal line. The MOS transistor circuit also includes a source follower type analog amplifier having an input electrode connected to the other one of the source and drain electrodes of the MOS transistor, one of plural power supply electrodes connected to the scanning line, and an output electrode connected to the pixel electrode.
1 . An active matrix-type liquid crystal display device comprising a pixel: electrode and a MOS transistor circuit, the pixel electrode being driven by the MOS transistor circuit, the MOS transistor circuit disposed in the vicinity of a cross-over point of one of a plurality of scanning lines and one of a plurality of signal lines, the MOS type transistor circuit comprising:
a first MOS transistor, in which a gate electrode is connected to the scanning line, and one of a source electrode and a drain electrode is connected to the signal line;
a second MOS transistor, in which a gate electrode is connected to the other one of the source electrode and the drain electrode of the first MOS transistor, one of a source electrode and a drain electrode is connected to the scanning line, and the other one of the source electrode and the drain electrode is connected to the pixel electrode; and
a resistor, one of two terminals of which is connected to the pixel electrode.
2 . An active matrix-type liquid crystal display device according to claim 1 , wherein the resistance value of the resistor is set to be less than the value of a resistance component which determines a response time constant of a liquid crystal in a pixel.
3 . An active matrix-type liquid crystal display device comprising a pixel electrode and a MOS transistor circuit, the pixel electrode being driven by the MOS transistor circuit, the MOS transistor circuit disposed in the vicinity of a cross-over point of one of a plurality of scanning lines and one of a plurality of signal lines, the MOS type transistor circuit comprising:
a first MOS transistor, in which a gate electrode is connected to an Nth scanning line, N being an integer of 2 or more, and one of a source electrode and a drain electrode is connected to the signal line;
a second electrode, in which a gate electrode is connected to the other one of the source electrode and the drain electrode of the first MOS transistor and one of a source electrode and a drain electrode is connected to a (N-1)th scanning line, and the other one of the source electrode and the drain electrode is connected to the pixel electrode; and
a resistor, in which one end of two terminals is connected to the pixel electrode.
4 . An active matrix-type liquid crystal display device according to claim 3 , wherein the resistance value of the resistor is set to be less than a value of a resistance component which determines a response time constant of a liquid crystal in a pixel.
5 . The method of driving the active matrix-type liquid crystal display device according to claim 2 , the method comprising the steps of:
in a scanning line selection period, storing the data signal in the gate electrode of the second MOS transistor by a scanning pulse signal through the first MOS transistor and resetting the second MOS transistor by transmitting the scanning pulse signal to the pixel electrode through the scanning MOS transistor; and
after completion of the scanning line selection period, writing signals corresponding to the stored data to the pixel electrode through the second MOS transistor, the resistor, or the third MOS transistor.
6 . The method of driving the active matrix-type liquid crystal display device according to claim 3 , comprising the steps of:
in the (N-1)th scanning line selection period, resetting the second MOS transistor by transmitting the (N-1)th scanning pulse signal to the pixel electrode through the second MOS transistor;
in the Nth scanning line selection period, storing a data signal in the second MOS transistor by the Nth scanning pulse signal through the first MOS transistor; and
after completion of the Nth scanning line selection period, writing signals corresponding to the stored data to the pixel electrode through the analog amplifier, the resistor, or the third MOS transistor.