Semiconductor devices and methods of manufacture thereof

1 . A semiconductor device, comprising:

a first transistor, the first transistor comprising at least one first gate electrode including a first metal layer; and

a second transistor, the second transistor comprising at least one second gate electrode including the first metal layer, wherein the at least one first gate electrode or the at least one second gate electrode includes a second metal layer disposed over the first metal layer.

2 . The semiconductor device according to claim 1 , wherein the second metal layer comprises a cap layer that affects a work function of the at least one first gate electrode of the first transistor or the at least one second gate electrode of the second transistor.

3 . The semiconductor device according to claim 1 , wherein the second metal layer comprises a different material than the first metal layer.

4 . The semiconductor device according to claim 3 , wherein the first metal layer and the second metal layer comprise TiSiN, TiN, TaCN, TaN, Ta, Ru, HfN, W, Al, RuTa, TaSiN, NiSi, CoSi x , TiSi x , Ir, Y, Pt, Ti, PtTi, Pd, Re, Rh, borides, phosphides, or antimonides of Ti, Hf, Zr, TiAlN, Mo, MoN, ZrSiN, ZrN, HfN, HfSiN, WN, Ni, Pr, VN, TiW, partially silicided materials thereof, fully silicided materials thereof, and/or combinations thereof.

5 . The semiconductor device according to claim 1 , wherein the first metal layer comprises TiSiN, and wherein the second metal layer comprises TaCN or TiN.

6 . The semiconductor device according to claim 1 , wherein the first metal layer of the at least one first gate electrode of the first transistor comprises the same thickness or a different thickness than the first metal layer of the at least one second gate electrode of the second transistor.

7 . A semiconductor device, comprising:

a first transistor, the first transistor comprising at least one first gate electrode including a first metal layer and a second metal layer disposed over the first metal layer; and

a second transistor, the second transistor comprising at least one second gate electrode including the first metal layer and a third metal layer disposed over the first metal layer, wherein the third metal layer comprises a different material than the second metal layer.

8 . The semiconductor device according to claim 7 , wherein the second metal layer comprises a first cap layer that affects a first work function of the at least one first gate electrode of the first transistor, and wherein the third metal layer comprises a second cap layer that affects a second work function of the at least one second gate electrode of the second transistor.

9 . The semiconductor device according to claim 7 , wherein the first metal layer, the second metal layer, and the third metal layer comprise a thickness of about 200 Angstroms or less.

10 . The semiconductor device according to claim 7 , wherein the at least one first gate electrode and the at least one second gate electrode include a layer of semiconductive material disposed over the second metal layer and third metal layer, respectively.

11 . The semiconductor device according to claim 7 , wherein the first transistor comprises a single gate electrode or multiple gate electrodes, and wherein the second transistor comprises a single gate electrode or multiple gate electrodes.

12 . The semiconductor device according to claim 7 , wherein the second metal layer and the third metal layer comprise the same thickness or different thicknesses.

13 . A semiconductor device, comprising:

a positive channel metal oxide semiconductor (PMOS) transistor, the PMOS transistor comprising at least one first gate electrode including a first metal layer and a second metal layer disposed over the first metal layer, the second metal layer comprising a different material than the first metal layer; and

a negative channel metal oxide semiconductor (NMOS) transistor, the NMOS transistor comprising at least one second gate electrode including the first metal layer and a third metal layer disposed over the first metal layer, the third metal layer comprising a different material than the second metal layer and the first metal layer.

14 . The semiconductor device according to claim 13 , wherein the second metal layer comprises a first cap layer that affects a first work function of the at least one first gate electrode of the PMOS transistor, wherein the third metal layer comprises a second cap layer that affects a second work function of the at least one second gate electrode of the NMOS transistor, wherein the first work function comprises about 4.5 to 4.9 eV, and wherein the second work function comprises about 4.2 to 4.6 eV.

15 . The semiconductor device according to claim 13 , wherein the PMOS transistor and the NMOS transistor comprise symmetric threshold voltage V t values of about +/−0.1 V to about +/−15V.

16 . The semiconductor device according to claim 13 , wherein the PMOS transistor and the NMOS transistor include a gate dielectric material disposed beneath the first metal layer, wherein the gate dielectric material comprises a hafnium-based dielectric, HfO 2 , HfSiO x , Al 2 O 3 , ZrO 2 , ZrSiO x , Ta 2 O 5 , La 2 O 3 , nitrides thereof, Si x N y , SiON, HfAlO x , HfAlO x N 1-x-y , ZrAlO x , ZrAlO x N y , SiAlO y , SiAlO x N 1-x-y , HfSiAlO x , HfSiAlO x N y , ZrSiAlO x , ZrSiAlO x N y , combinations thereof, combinations thereof with SiO 2 , or SiO 2 .

17 . A method of manufacturing a semiconductor device, the method comprising:

providing a workpiece, the workpiece having a first region and a second region;

forming a gate dielectric material over the workpiece;

forming a first metal layer over the gate dielectric material;

forming a second metal layer over the first metal layer;

removing at least a portion of the second metal layer in the second region; and

patterning the second metal layer, the first metal layer, and the gate dielectric material to form a first transistor in the first region and a second transistor in the second region.

18 . The method according to claim 17 , wherein removing at least a portion of the second metal layer in the second region comprises reducing the thickness of the second metal layer in the second region.

19 . The method according to claim 17 , wherein removing at least a portion of the second metal layer in the second region comprises removing all of the second metal layer in the second region.

20 . The method according to claim 19 , further comprising forming a third metal layer over the second metal layer in the first region and over the first metal layer in the second region, wherein patterning the second metal layer, the first metal layer and the gate dielectric material further comprises patterning the third metal layer.

21 . The method according to claim 20 , further comprising removing at least a portion of the third metal layer from over the second metal layer in the first region.

22 . The method according to claim 21 , wherein removing at least a portion of the third metal layer from over the second metal layer in the first region comprises removing all of the third metal layer from over the second metal layer in the first region.

23 . The method according to claim 21 , wherein removing at least a portion of the third metal layer from over the second metal layer in the first region comprises reducing the thickness of the third metal layer in the first region.

24 . The method according to claim 17 , wherein the first transistor comprises a first CMOS device, wherein the second transistor comprises a second CMOS device, wherein the first CMOS device comprises a first device type, wherein the second CMOS device comprises a second device type, wherein the second device type is different from the first device type, and wherein the first device type and the second device type comprise a high performance (HP) device, a low operation power (LOP) device, or a low standby power (LSTP) device.

25 . The method according to claim 17 , wherein providing the workpiece comprises providing a silicon-on-insulator (SOI) substrate having a substrate, a buried insulating layer disposed over the substrate, and a layer of semiconductor material disposed over the buried insulating layer, further comprising, before forming the gate dielectric material over the workpiece:

forming at least one first fin structure and at least one second fin structure within the layer of semiconductor material disposed over the buried insulating layer of the SOI substrate within the first region and second region of the workpiece, respectively, each of the at least one first fin structure and each of the at least one second fin structure comprising a first sidewall and an opposing second sidewall, wherein forming the gate dielectric material comprises forming the gate dielectric material over at least the first and second sidewalls of the at least one first fin structure and the at least one second fin structure, wherein patterning the second metal layer, the first metal layer, and the gate dielectric material comprising forming at least two first gate electrodes in the first region and forming at least two second gate electrodes in the second region, wherein the at least two first gate electrodes, the gate dielectric material, and the at least one first fin structure comprise the first transistor, and wherein the at least two second gate electrodes, the gate dielectric material, and the at least one second fin structure comprise the second transistor.

26 . The method according to claim 25 , wherein patterning the second metal layer, the first metal layer, and the gate dielectric material comprise forming a plurality of first transistors in the first region and a plurality of second transistors in the second region.