Semiconductor device with NMOS transistors arranged continuously
View Patent ↗A semiconductor device includes a plurality of PMOS transistors formed on a semiconductor substrate; and a plurality of NMOS transistors formed on the semiconductor substrate. The plurality of PMOS transistors are electrically isolated from each other by a device isolation structure formed in the semiconductor substrate. The plurality of NMOS transistors are continuously formed in a first direction such that a sequence of N-type diffusion layers of the plurality of NMOS transistors extends in the first direction. One of the plurality of PMOS transistors and one of the plurality of NMOS transistors share a gate electrode.
1. A semiconductor device comprising:
a plurality of PMOS transistors formed on a semiconductor substrate;
a plurality of NMOS transistors formed on said semiconductor substrate; and
a gate structure formed on said semiconductor substrate between an adjacent of said plurality of NMOS transistors to extend in a second direction perpendicular to a first direction over an N-type diffusion layer,
wherein said plurality of PMOS transistors are surrounded and electrically isolated from each other by a device isolation structure formed in said semiconductor substrate,
wherein said plurality of NMOS transistors are adjacent to each other and surrounded by said device isolation structure in said first direction such that said N-type diffusion layer of said plurality of NMOS transistors extends continuously with respect to said plurality of NMOS transistors in said first direction, and
wherein one of said plurality of PMOS transistors and one of said plurality of NMOS transistors share a gate electrode.
2. The semiconductor device according to claim 1 , wherein a ground voltage is applied to said gate structure.
3. The semiconductor device according to claim 1 , wherein a power supply voltage is applied to said gate structure.
4. The semiconductor device according to claim 1 , wherein said gate structure isolates a predetermined number of said plurality of said NMOS transistors.
5. The semiconductor device according to claim 4 , wherein the predetermined number is two.
6. The semiconductor device according to claim 4 , wherein the predetermined number is four.
7. The semiconductor device according to claim 4 , wherein the predetermined number is six.
8. The semiconductor device according to claim 5 , wherein said gate electrode of said one of said plurality of NMOS transistors is connected to another gate electrode of another one of said plurality of NMOS transistors.
9. The semiconductor device according to claim 6 , wherein four of said gate electrodes of four of said plurality of NMOS transistors are connected to each other.
10. The semiconductor device according to claim 1 , wherein said device isolation structure is formed between each of said plurality of PMOS transistors.
11. The semiconductor device according to claim 1 , wherein each of said plurality of PMOS transistors comprises a P-type diffusion layer.
12. The semiconductor device according to claim 11 , wherein a length of said N-type diffusion layer is greater than a length of said P-type diffusion layer.
13. The semiconductor device according to claim 1 , wherein said plurality of NMOS transistors comprises an NMOS transistor group, and
wherein said N-type diffusion layer extends throughout said NMOS transistor group in said first direction.
14. The semiconductor device according to claim 1 , wherein said gate structure is connected to one of a ground line and a P-type diffusion layer connected to said ground line.