IP Library › Patent Application 11434383
Patent Application
App. No. 11/434,383

Method for making tapered opening for programmable resistance memory element

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Quick Facts
Patent No.
US None
App. No.
11/434,383
Abstract

A method for making a tapered opening. The defined tapered opening is useful for the fabrication of programmable resistance memory elements. The programmable resistance memory material may be a chalcogenide.

Claims (35)

1 . A method of fabricating a second opening, comprising:

providing a layer of a first material;

forming a layer of a second material over said layer of said first material;

forming a layer of a third material over said layer of said second material;

forming a first opening in said layer of said third material to expose said second material;

forming a sidewall spacer of a fourth material on a sidewall surface of said first opening;

removing a portion of said layer of said second material to form a recess in said layer of said second material; and

removing said third material, said fourth material and an additional portion of said second material to form said second opening in said layer of said second material to expose said first material.

2 . The method of claim 1 , wherein said second opening is a hole.

3 . The method of claim 1 , wherein said second opening is a trench.

4 . The method of claim 1 , wherein said first opening in said third material does not extend into substantially any of said layer of said second material.

5 . The method of claim 1 , wherein said first opening in said third material extends partially into said layer of said second material.

6 . The method of claim 1 , wherein third material and said fourth material are the same material.

7 . The method of claim 1 , wherein said first material is a conductive material.

8 . The method of claim 1 , wherein said second material is a dielectric.

9 . The method of claim 8 , wherein said dielectric comprises an oxide or a nitride.

10 . The method of claim 1 , wherein said third material and said fourth material are polysilicon.

11 . The method of claim 1 , wherein said third material and said fourth material are a dielectric.

12 . The method of claim 11 , wherein said dielectric is an oxide or a nitride.

13 . The method of claim 1 , wherein the rates of removal of said third and fourth materials are each greater than the rate of removal of said additional second material.

14 . The method of claim 1 , wherein the ratio of the depth of said recess of said second layer to the thickness of said second layer is less than 0.5.

15 . A method of fabricating a memory element, comprising:

providing a layer of a first material;

forming said layer of said second material over said layer of said first material;

forming a layer of a third material over said layer of said second material;

forming an opening in said layer of said third material to expose said second material;

forming a sidewall spacer of a fourth material on a sidewall surface of said opening;

removing a portion of said second material to form a recess in said layer of said second material;

removing said third material, said fourth material and an additional portion of said layer of said second material to form an opening in said layer of said second material to expose said first material; and

forming a programmable resistance material in said opening of said second material.

16 . The method of claim 15 , wherein said opening in said third material does not extend into substantially any of said layer of said second material.

17 . The method of claim 15 , wherein said opening in said third material extends partially into said layer of said second material.

18 . The method of claim 15 , wherein third material and said fourth material are the same material.

19 . The method of claim 15 , wherein the rates of removal of said third and fourth materials are each greater than the rate of removal of said additional second material.

20 . The method of claim 15 , wherein the ratio of the depth of said recess of said second layer to the thickness of said second layer is less than 0.5.