Scanning imager employing multiple chips with staggered pixels
View Patent ↗A solid state imaging system has at least one CMOS imager with first and second series of pixels in which the pixels of one series are offset, i.e., staggered, in respect to the pixels of the other series. Multiple imagers can be arrayed end to end, with jumper wires connecting the pixel output conductors or each so that the pixels feed into a common output amplifier for each series, to minimize chip to chip offset voltages. The pixels may be diagonally offset from one another, and a color imager can be constructed in which color ribbon filters are arranged diagonally across the imaging area. This arrangement minimizes color cross talk.
1. A system for scanning an image, comprising:
a plurality of CMOS imagers arranged end to end, each said CMOS imager including
two series of pixels situated alongside one another and wherein one of the series of pixels is offset from the other of the series of pixels;
two pairs of conductors extending along said series of pixels, with the pairs of conductors being associated with the respective series of pixels on said CMOS imager, and wherein
each said pixel includes a respective pixel amplifier FET having a source electrode and a drain electrode which are respectively coupled to the conductors of the associated pair of conductors and in parallel to all other pixel amplifier FETs of said series;
a plurality of jumper conductors connecting the conductors of each said pair of conductors of each said CMOS imager with the corresponding conductors of the remaining imagers;
a pair of output amplifiers each including an additional FET and a feedback path coupled to a respective pair of conductors of at least one of said CMOS imagers;
image control circuitry coupled to the series of pixels of said imagers; and
image focusing means for forming an optical image onto said plurality of imagers.
2. The system as set forth in claim 1 wherein each said series of pixels includes a unitary differential amplifier having a plurality of first input transistors that are located at respective pixels within the series, and a second input transistor common to the pixels of that series and connected to the first input transistors so as to create a feedback loop.
3. The system as set forth in claim 1 wherein said image control circuitry comprises shutter controller means for controlling integration times of the pixels for the respective pixels in at least one of said series of pixels.
4. The system as set forth in claim 1 wherein said image control circuitry comprises resolution adjustment means for selectively skipping read out of one or more of the pixels in at least one of said series of pixels so as to permit reduction of resolution and increase of frame rate.
5. The system as set forth in claim 1 wherein the pixels of each said series of pixels are arranged in pairs or pixel regions arranged diagonally on two sides of a pixel control region such that the pairs of pixel regions each extend diagonally defining diagonal zones between successive pairs of pixel regions of that series, and wherein the pixels of the other series of pixels are situated within said diagonal zones.
6. The system as set forth in claim 5 wherein said pixel regions are divided into red, blue and green photosensitive areas, such that the red, blue, and green photosensitive areas are aligned diagonally with the corresponding photosensitive areas of the pixel region that is disposed opposite said pixel control regions, and wherein red, blue and green optical filters are disposed as ribbon filters extending diagonally across the respective pixels' photosensitive areas.
7. The system as set forth in claim 1 , further comprising lens means for focusing an image of an object onto said plurality of CMOS imagers.