Apparatus and method for a programmable security processor
View Patent ↗A digital logic circuit comprises a programmable logic device and a programmable security circuit. The programmable security circuit stores a set of authorized configuration security keys. The programmable security circuit compares the authorized configuration security keys with an incoming configuration request, and selectively enables a new configuration for the programmable logic device in response to the configuration request. In another exemplary embodiment, a programmable security circuit also stores a set of authorized operation security keys. The programmable security circuit compares the authorized operation security keys with an incoming operation request from the programmable logic device, and selectively enables an operation within the programmable logic device in response to the operation request.
1. A method for configuring a reconfigurable processor having a plurality of hardware data processing elements, the method comprising:
receiving, at a repository, an algorithm across a network;
creating a configuration table based at least in part on the algorithm;
defining a functionality of at least one of the hardware data processing elements in a respective internal table based on the configuration table;
and configuring the at least one of the hardware data processing elements based on the defined functionality.
2. The method according to claim 1 , wherein the configuration table comprises security algorithms and data processing functions pertinent to the security algorithms.
3. The method according to claim 2 , wherein the security algorithms are selected from the group of security algorithms consisting of AES, DES, RSA, MISTY, and IDEA.
4. The method according to claim 1 , wherein the method is performed in a multi-standard mobile communications terminal.
5. The method according to claim 1 , further comprising transmitting parameters from the configuration table through an application programming interface and a virtual machine interface to the hardware data processing elements.
6. A system for implementing a security algorithm, the system comprising:
a reconfigurable security processor comprising hardware data processing elements,
wherein each of the hardware data processing elements and its interconnections are reconfigurable based on a security algorithm received across a network, and
wherein each of the hardware data processing elements comprises an internal table defining the functionality of the respective hardware data processing element based on the received security algorithm.
7. The system according to claim 6 , further comprising a software processing unit coupled to the reconfigurable security processor by a communication bus.
8. The system according to claim 7 , wherein the software processing unit comprises:
a digital signal processor; and
a control microprocessor.
9. The system according to claim 8 , wherein each of the hardware data processing elements is configured to perform computationally intensive data processing functions, and the digital signal processor is configured to perform less computationally intensive data processing functions relative to the hardware data processing elements.
10. The system according to claim 6 , wherein the security algorithm is selected from the group of security algorithms consisting of AES, DES, RSA, MISTY, and IDEA.
11. The system according to claim 6 , wherein the content of each of the internal tables is set by the reconfigurable security processor in accordance with the received security algorithm.