Process for producing thin film transistor having LDD region

1. A process for producing a thin film transistor display comprising steps of:

providing a substrate;

forming a polysilicon layer on said substrate;

patterning said polysilicon layer to define a first and a second TFT regions;

providing a first and a second doping masks on said polysilicon layer in said first and said second TFT regions to result in a first exposed portion in said first TFT region and a second exposed portion in said second TFT region;

implanting a first doping material into said first and said second exposed portions, thereby defining a first doped region and a first channel region adjacent to said first doped region in said first TFT region, and a second doped region and a second channel region adjacent to said second doped region in said second TFT region;

removing said first doping mask without removing said second doping mask;

providing a third doping mask on said first channel region, which partially overlies said first doped region, so as to result in a third exposed portion in said first TFT region smaller than said first exposed portion;

implanting a second doping material into said third exposed portions and said second exposed portion to form first source/drain regions and second source/drain regions and simultaneously define a first LDD region;

removing said second doping mask along with said third doping mask;

forming an insulator layer and a gate metal layer on the resulting structure; and

patterning said gate metal layer to form a first and a second gate structures over said first and said second channel regions, respectively,

wherein in a certain direction, said first gate structure is longer than said first channel, and said second gate structure has length no greater than the length of said second channel region.

2. The process according to claim 1 wherein the length of said second gate structure is substantially identical to the length of said second channel region in said certain direction.

3. The process according to claim 1 wherein said first, said second and said third doping masks are photoresists.

4. The process according to claim 1 further comprising a step of doping said patterned polysilicon layer in order to define said first and second TFT regions.

5. The process according to claim 1 further comprising a step of implanting a third doping material into said second TFT region with said second gate structure serving as a doping mask to form a second LDD region.

6. The process according to claim 1 further comprising a step of covering a portion of said patterned polysilicon layer with a fourth doping mask before doping said patterned polysilicon layer for further defining a third TFT region.

7. The process according to claim 6 wherein said first TFT region is an N-channel TFT region of a driving circuit, said second TFT region is an N-channel TFT region of an active matrix, and said third TFT region is a P-channel TFT region.

8. The process according to claim 7 wherein said fourth doping mask is removed along with said second and said third doping masks.

9. The process according to claim 8 further comprising steps of:

forming a third gate structure over said third TFT region at the same time when said first and said second gate structures are formed; and

implanting a third doping material into said third TFT region with said third gate region serving as a mask to form source/drain regions of said third TFT region.