LCD panel and fabricating method with ball spacer within dummy source/drain electrode pattern and dummy semiconductor pattern over gate line for maintaining cell gap

1. A liquid crystal display panel, comprising:

an upper substrate;

a lower substrate facing the upper substrate;

a gate line and a data line on an upper surface of the lower substrate facing the upper substrate, the gate line and the data line cross each other to define a cell area;

a pixel electrode formed in the cell area;

a dummy source/drain electrode pattern over the gate line; and

a ball spacer within the dummy source/drain electrode pattern, the ball spacer maintaining a cell gap between the upper substrate and the lower substrate.

2. The liquid crystal display panel according to claim 1 , further comprising a thin film transistor including:

a gate electrode connected to the gate line

an active layer over the gate electrode;

first and second ohmic contact layers on the active layer;

a source electrode on the first ohmic contact layer and connected to the data line; and

a drain electrode on the second ohmic contact layer and connected to the pixel electrode.

3. The liquid crystal display panel according to claim 2 , wherein the dummy source/drain electrode pattern is formed of the same material as the source electrode and the drain electrode of the thin film transistor.

4. The liquid crystal display panel according to claim 2 , further comprising a dummy semiconductor pattern between the dummy source/drain electrode pattern and the gate line.

5. The liquid crystal display panel according to claim 4 , wherein the dummy source/drain electrode pattern and the dummy semiconductor pattern have the same shape.

6. The liquid crystal display panel according to claim 1 , further comprising a common electrode formed on the lower substrate.

7. The liquid crystal display panel according to claim 1 , further comprising a common electrode formed on the upper substrate.

8. A liquid crystal display panel, comprising:

an upper substrate;

a lower substrate facing the upper substrate;

a gate line and a data line on an upper surface of the lower substrate facing the upper substrate, the gate line and the data line cross each other to define a cell area;

a pixel electrode formed in the cell area;

a dummy semiconductor pattern over the gate line; and

a ball spacer within the dummy semiconductor pattern, the ball spacer maintaining a cell gap between the upper substrate and the lower substrate.

9. The liquid crystal display panel according to claim 8 , further comprising a thin film transistor including:

a gate electrode connected to the gate line;

an active layer over the gate electrode;

first and second ohmic contact layers on the active layer;

a source electrode on the first ohmic contact layer and connected to the data line; and

a drain electrode on the second ohmic contact layer and connected to the pixel electrode.

10. The liquid crystal display panel according to claim 9 , wherein the dummy semiconductor pattern is formed of the same materials as the first and second ohmic contact layers, and the active layer of the thin film transistor.

11. The liquid crystal display panel according to claim 8 , further comprising a common electrode formed on the lower substrate.

12. The liquid crystal display panel according to claim 8 , further comprising a common electrode formed on the upper substrate.

13. A fabricating method of a liquid crystal display panel, comprising:

forming a gate line on a lower substrate;

forming a data line crossing the gate line, and a first dummy pattern on the gate line;

forming a pixel electrode in a pixel area defined by the crossing of the gate line and the data line;

depositing a ball spacer within the first dummy pattern; and

providing an upper substrate facing the upper substrate;

bonding an upper substrate to the lower substrate.

14. The fabricating method according to claim 13 , further comprising:

forming a gate electrode connected to the gate line;

forming an active layer over the gate electrode;

forming first and second ohmic contact layers on the active layer;

forming a source electrode on the first ohmic contact layer; and

forming a drain electrode on the second ohmic contact layer.

15. The fabricating method according to claim 14 , wherein the first dummy pattern is formed of the same material as the source electrode and the drain electrode.

16. The fabricating method according to claim 15 , wherein the first dummy pattern is formed at the same time as the source electrode and the drain electrode.

17. The fabricating method according to claim 14 , wherein the first dummy pattern is formed of the same material as the first and second ohmic contact layers, and the active layer.

18. The fabricating method according to claim 14 , wherein the first dummy pattern is formed at the same time as the first and second ohmic contact layers, and the active layer.

19. The fabricating method according to claim 14 , further comprising:

forming a second dummy pattern between the first dummy pattern and the gate line.

20. The fabricating method according to claim 19 , wherein the second dummy pattern is formed of the same material as the first and second ohmic contact layers, and the active layer.

21. The fabricating method according to claim 20 , wherein the second dummy pattern is formed at the same time as the first and second ohmic contact layers, and the active layer of.

22. The fabricating method according to claim 19 , wherein the first dummy pattern and the second dummy pattern are formed in the same mask processing step.

23. The fabricating method according to claim 22 , wherein the mask processing step uses a half-tone mask.

24. The fabricating method according to claim 13 , further comprising:

forming a common electrode on the lower substrate.

25. The fabricating method according to claim 13 , further comprising:

forming a common electrode on the upper substrate.