Semiconductor device with non-volatile memory and random access memory
View Patent ↗A semiconductor device including a large capacity non-volatile memory and at least one random access memory, said the access time of said device being matched to the access time of each random access memory. The semiconductor memory device is comprised of: a non-volatile memory FLASH having a first reading time; a random access memory DRAM having a second reading time which is more than 100 times shorter than the first reading time; a circuit that includes a control circuit connected to both the FLASH and the DRAM and enabled to control accesses to those FLASH and DRAM; and a plurality of I/O terminals connected to the circuit. As a result, FLASH data is transferred to the DRAM before the DRAM is accessed, thereby matching the access time between the FLASH and the DRAM. Data is written back from the DRAM to the FLASH as needed, thereby keeping data matched between the FLASH and the DRAM and storing the data.
1. A memory module comprising:
a plurality of first terminals for inputting a plurality of command signals from outside of the memory module;
a plurality of second terminals for inputting an address from outside of the memory module;
a plurality of third terminals for inputting a plurality of data from outside of the memory module;
a non-volatile memory;
a random access memory for reading data out to outside of the memory module via the plurality of third terminals;
a command register into which is written load instruction code, the load instruction code being inputted from outside of the memory module via the plurality of third terminals; and
an error correction circuit for checking whether or not data read from the non-volatile memory contains any error and correcting the error when detected,
further wherein when the load instruction code is written into the command register, the data stored in the non-volatile memory is transferred from the non-volatile memory to the random access memory via the error correction circuit, and
further wherein the random access memory outputs the data after correcting the error by the error correction circuit from the plurality of third terminals when the memory module is accessed to read out data.
2. A memory module according to claim 1 ,
wherein the memory module selects the command register or the random access memory according to the address inputted to the plurality of second terminals when the write instruction is inputted to the plurality of first terminals.
3. A memory module according to claim 2 , further comprising:
a controller generating control signals to control the non-volatile memory,
wherein the controller generates the control signal when the load instruction code is written into the command register.
4. A memory module according to claim 1 ,
wherein when the memory module is inputted the address which indicates the non-volatile memory to the plurality of second terminals and a read instruction to the plurality of first terminals, the random access memory outputs the data transferred from non-volatile memory.
5. A memory module according to claim 1 ,
wherein the random access memory is a dynamic random access memory, and
further wherein a capacitance of the dynamic random access memory is equal to or larger than a capacitance of the non-volatile memory.
6. A memory module according to claim 5 ,
wherein the memory module uses a SDRAM interface.
7. A memory module according to claim 1 ,
wherein the memory module uses a SRAM interface.