IP Library Granted Patent US 7,598,459
Granted Patent B2
US 7,598,459 · App. 11/439,417 · Granted Oct 6, 2009

Electronic board, method of manufacturing the same, and electronic device

View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 7,598,459
App. No.
11/439,417
Granted
Oct 6, 2009
Kind
B2
Abstract

An electronic board includes: a substrate on which is formed an electronic circuit having a connection terminal; a stress-relaxation layer formed on the substrate; rearrangement wiring for the connection terminal disposed at a top side of the stress-relaxation layer; and a capacitor that has a first electrode that is disposed between the substrate and the stress-relaxation layer, a second electrode that is disposed at the top side of the stress-relaxation layer, and a dielectric material that is disposed between the first electrode and the second electrode.

Claims (11)

1. An electronic board comprising:

a substrate;

an electronic circuit on the substrate, the electronic circuit having connection terminals;

a stress-relaxation layer on the substrate, the stress-relaxation layer being formed of a dielectric material;

a rearrangement wiring for the connection terminal, the rearrangement wiring being disposed at a top side of the stress-relaxation layer;

a first wiring that extends from one of the connection terminals, the one of the connection terminals being disposed lateral to the stress-relaxation layer, a part of the first wiring being covered by the stress-relaxation layer, another part of the first wiring not being covered by the stress-relaxation layer;

a first electrode disposed between the substrate and the stress-relaxation layer, the first electrode being at least a portion of the part of the first wiring;

a second wiring that extends from another one of the connection terminals, the another one of the connection terminals being disposed lateral to the stress-relaxation layer, at least a part of the second wiring being disposed at the top side of the stress-relaxation layer;

a second electrode disposed at the top side of the stress-relaxation layer, the second electrode being at least a portion of the part of the second wiring; and

a capacitor including the first electrode, a part of the stress-relaxation layer, and the second electrode, the capacitor being formed at a region where the first wiring and the second wiring overlap in a plan view,

wherein the second wiring is a part of the rearrangement wiring.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 27, 2020
From: SEIKO EPSON CORPORATION
To: 138 EAST LCD ADVANCEMENTS LIMITED
Reel/Frame 051707/0399 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 23, 2006
From: HASHIMOTO, NOBUAKI
To: SEIKO EPSON CORPORATION
Reel/Frame 017930/0906 →