Method for reducing substrate noise from penetrating noise sensitive circuits
A CMOS device includes a p-type substrate and an isolated PWell region. An isolation region has an NWell region abutting a perimeter of the PWell region. The isolation region includes a DNWell region positioned below the PWell region and an NWell region. The NWell region forms a sidewall of a tub and the DNWell region forms a bottom of the tub. The tub is an n-type region that physically and electrically isolates an enclosed PWell region from the p-type substrate. A NTN region is formed in the p-type substrate and at least partially abuts an outer perimeter of the NWell region. The NTN region is defined as a non-PWell and a non-NWell region. The NTN region enhances electrical isolation of the circuits inside the PWell region from circuits outside of the PWell region. In one embodiment, the high-frequency performance of an NMOSFET inside the isolated PWell is improved because of the reduced sidewall capacitance with the NTN region.
1 . A CMOS device, comprising:
a p-type substrate;
a PWell region;
an isolation region that includes an NWell region abutting a perimeter of the PWell region, the isolation region including a DNWell region positioned below the PWell region and an NWell region, the NWell region forming a sidewall of a tub and the DNWell region forming a bottom of the tub, the tub being an n-type region that physically and electrically isolates an enclosed PWell region from the p-type substrate;
a NTN region formed in the p-type substrate and at least partially abutting an outer perimeter of the NWell region;
wherein the NTN region enhances the electrical isolation of the circuits inside the isolated PWell region from the circuits outside of the isolated PWell region.
2 . The device of claim 1 , wherein the NTN region is defined as a non-PWell and a non-NWell region.
3 . The device of claim 1 , wherein the NTN region is defined as a region without PWell implants and without the NWell implants.
4 . The device of claim 1 , wherein the circuits may include IC transistors, such as MOSFETs and bipolar transistors, or passive devices, such as IC resistors, capacitors, and inductors.
5 . The device of claim 1 , wherein the NTN region increases impedance of PN junctions formed by the NWell and DNWell regions to the surrounding p-type substrate.
6 . The device of claim 5 , wherein the NTN region provides an enhanced level of electrical noise isolation.
7 . The device of claim 1 , wherein the NTN region has a lowered substrate doping than the PWell region.
8 . The device of claim 7 , wherein the doping of the NTN region is no more than about 10% of the doping of the PWell region or the NWell region, whichever has the lower doping.
9 . The device of claim 8 , wherein the NTN region increases an effective resistance in series with the PN junctions due to a lowered substrate doping.
10 . The device of claim 1 , wherein the NWell region has a decreased sidewall capacitance.
11 . The device of claim 1 , wherein a lower perimeter capacitance of the NWell perimeter improves a higher frequency performance of an NMOSFET inside the PWell region.
12 . The device of claim 1 , wherein the PWell region acts as a channel-stop.
13 . The device of claim 1 , wherein the PWell region acts as a channel-stop that breaks the formation of the parasitic native field-oxide NMOSFET.
14 . The device of claim 1 , further comprising:
at least one circuit inside the enclosed PWell region; and
at least one circuit external to the NWell region.
15 . The device of claim 14 , wherein the at least one circuit inside the PWell region includes a mosfet or a passive device.
16 . The device of claim 14 , wherein the at least one circuit external to the NWell region includes a mosfet or a passive device.
17 . A CMOS device, comprising:
a n-type substrate;
a NWell region;
an isolation region that includes an PWell region abutting a perimeter of the NWell region, the isolation region including a Deep-PWell region positioned below the NWell region and a PWell region, the PWell region forming a sidewall of a tub and the Deep-PWell region forming a bottom of the tub, the tub being a p-type region that physically and electrically isolates an enclosed NWell region from the n-type substrate;
a NTN region formed in the n-type substrate and at least partially abutting an outer perimeter of the PWell region; and
wherein the NTN region enhances the electrical isolation of the circuits inside the isolated NWell region from the circuits outside the isolated NWell region.
18 . The device of claim 17 , wherein the NTN region is defined as a non-PWell and a non-NWell region.
19 . The device of claim 17 , wherein the NTN region is defined as a region without PWell implants and without the NWell implants.
20 . A CMOS device, comprising:
a p-type substrate;
an NWell region;
a NTN region formed in the p-type substrate and at least partially abutting an outer perimeter of the NWell region;
wherein the NTN region enhances the electrical isolation of the circuits inside the NWell region from circuits outside the NWell region.
21 . The device of claim 20 , wherein the NTN region is defined as a non-PWell and a non-NWell region.
22 . The device of claim 20 , wherein the NTN region is defined as a region without PWell implants and without the NWell implants.
23 . A CMOS device, comprising:
an n-type substrate;
a PWell region;
a NTN region formed in the n-type substrate and at least partially abutting an outer perimeter of the PWell region; and
wherein the NTN region enhances the electrical isolation of the circuits inside the PWell region from circuits outside the PWell region.
24 . The device of claim 23 , wherein the NTN region is defined as a non-PWell and a non-NWell region.
25 . The device of claim 23 , wherein the NTN region is defined as a region without PWell implants and without the NWell implants.