CMOS shared amplifier pixels with output signal wire below floating diffusion interconnect for reduced floating diffusion capacitance
View Patent ↗An image sensor includes a unit cell having a plurality of pixels; the unit cell comprising an amplifier input transistor that is shared by the plurality of pixels; a plurality of floating diffusions that are joined by a floating diffusion interconnect layer and are connected to the amplifier input transistor; and an interconnect layer which forms an output signal wire which shields the floating diffusion interconnect layer.
1. An image sensor comprising:
a unit cell having a plurality of pixels; the unit cell comprising:
(a) an amplifier input transistor that is shared by the plurality of pixels;
(b) a plurality of floating diffusions that are joined by a floating diffusion interconnect layer and are connected to the amplifier input transistor; and
(c) a row select transistor electrically connected to an output signal wire,
wherein the floating diffusion interconnect layer is positioned directly over a portion of the output signal wire to shield the floating diffusion interconnect layer.
2. An image sensor comprising:
a unit cell having a plurality of pixels, each pixel comprising a photodetector comprising an n-type implant and a transfer gate; the unit cell comprising:
(a) an nMOS transistor comprising an n-type source drain implant disposed in a P well;
(b) a plurality of floating diffusions that are joined by a floating diffusion interconnect layer;
wherein the plurality of floating diffusions each have an n-type source drain implant and a deeper n-type implant that is more lightly doped than the floating diffusion n-type source drain implant with the deeper n-type implant enclosing the floating diffusion n-type source drain implant, wherein the floating diffusion n-type source drain implants and the deeper n-type implants are not disposed in the P well and the photodetector n-type implants and the deeper n-type implants are formed by the same implant; and
(c) a row select transistor electrically connected to an output signal wire,
wherein the floating diffusion interconnect layer is positioned directly a portion of the output signal wire to shield the floating diffusion interconnect layer.
3. An image sensor comprising:
a unit cell having a plurality of pixels, each pixel comprising a photodetector comprising an n-type implant and a transfer gate; the unit cell comprising:
(a) a plurality of floating diffusions having n-type source drain implants, and the floating diffusions are joined by a floating diffusion interconnect layer; wherein a deeper n-type implant that is more lightly doped than the n-type source drain implant encloses at least one of the n-type source drain implants for reducing junction capacitance, and wherein the photodetector n-type implants and the deeper n-type implants are formed by the same implant; and
(b) a row select transistor electrically connected to an output signal wire,
wherein the floating diffusion interconnect layer is positioned directly over a portion of the output signal wire to shield the floating diffusion interconnect layer.
4. A camera comprising:
an image sensor comprising:
a unit cell having a plurality of pixels; the unit cell comprising:
(a) an amplifier input transistor that is shared by the plurality of pixels;
(b) a plurality of floating diffusions that are joined by a floating diffusion interconnect layer and are connected to the amplifier input transistor; and
(c) a row select transistor electrically connected to an output signal wire,
wherein the floating diffusion interconnect layer is positioned directly over a portion of the output signal wire to shield the floating diffusion interconnect layer.
5. A camera comprising:
an image sensor comprising:
a unit cell having a plurality of pixels, each pixel comprising a photodetector comprising an n-type implant and a transfer gate; the unit cell comprising:
(a) an nMOS transistor comprising an n-type source drain implant disposed in a P well;
(b) a plurality of floating diffusions that are joined by a floating diffusion interconnect layer;
wherein the plurality of floating diffusions each have an n-type source drain implant and a deeper n-type implant that is more lightly doped than the floating diffusion n-type source drain implant with the deeper n-type implant enclosing the floating diffusion n-type source drain implant, wherein the floating diffusion n-type source drain implants and the deeper n-type implants are not disposed in the P well and the photodetector n-type implants and the deeper n-type implants are formed by the same implant; and
c) a row select transistor electrically connected to an output signal wire,
wherein the floating diffusion interconnect layer is positioned directly a portion of the output signal wire to shield the floating diffusion interconnect layer.
6. A camera comprising:
an image sensor comprising:
a unit cell having a plurality of pixels, each pixel comprising a photodetector comprising an n-type implant and a transfer gate; the unit cell comprising:
(a) a plurality of floating diffusions having n-type source drain implants, and the floating diffusions are joined by a floating diffusion interconnect layer; wherein a deeper n-type implant that is more lightly doped than the n-type source drain implant encloses at least one of the n-type source drain implants for reducing junction capacitance, and wherein the photodetector n-type implants and the deeper n-type implants are formed by the same implant; and
(b) a row select transistor electrically connected to an output signal wire,
wherein the floating diffusion interconnect layer is positioned directly over a portion of the output signal wire to shield the floating diffusion interconnect layer.