IP Library Granted Patent US 7,564,293
Granted Patent B2
US 7,564,293 · App. 11/443,064 · Granted Jul 21, 2009

Signal conversion circuit

View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 7,564,293
App. No.
11/443,064
Granted
Jul 21, 2009
Kind
B2
Abstract

A signal conversion circuit for converting an inputted differential signal into a single-ended signal comprises a differential amplifier circuit for amplifying the differential signal, and generating a first non-inverted signal and a first inverted signal being inverted the first non-inverted signal, a first inverter for generating a second non-inverted signal being inverted the first inverted signal and an interpolation unit for interpolating a phase difference between the first non-inverted signal and the second non-inverted signal.

Claims (53)

1. A signal conversion circuit for converting an inputted differential signal into a single-ended signal, comprising:

a differential amplifier circuit for amplifying the differential signal, and generating a first non-inverted signal and a first inverted signal being inverted the first non-inverted signal;

a first inverter for generating a second non-inverted signal being inverted the first inverted signal; and

an interpolation unit for interpolating a phase difference between the first non-inverted signal and the second non-inverted signal,

wherein the interpolation circuit comprises:

a first interpolation inverter for inverting the first non-inverted signal;

a second interpolation inverter for inverting the second non-inverted signal;

a third interpolation inverter for inverting depending on a charge/discharge of the capacitor; and

a capacitor for charging/discharging depending on an output signal from the first and the second interpolation inverters.

2. The signal conversion circuit according to claim 1 , wherein the differential amplifier circuit comprises:

a first differential pair for generating the first non-inverted signal; and

a second differential pair for generating the first inverted signal.

3. The signal conversion circuit according to claim 2 , wherein the first and the second differential pairs comprise:

a first transistor inputted one signal of the differential signal to a control terminal;

a second transistor connected in series to the first transistor;

a third transistor inputted another signal of the differential signal to a control terminal; and

a fourth transistor connected in series to the third transistor to form a current mirror with the second transistor,

wherein the first non-inverted signal or the first inverted signal is outputted from an intermediate node between the third transistor and the fourth transistor.

4. The signal conversion circuit according to claim 1 , wherein the differential amplifier circuit comprises a differential pair for outputting the first non-inverted signal from one output terminal and outputting the first inverted signal from another output terminal.

5. The signal conversion circuit according to claim 4 , wherein the differential amplifier circuit comprises two differential pair circuits, one differential pair circuit outputting a first non-inverted signal and a second differential pair circuit outputting a first inverted signal, and each differential pair circuit comprises:

a first transistor inputted one signal of the differential signal to a control terminal;

a second transistor connected in series to the first transistor;

a third transistor inputted another signal of the differential signal to a control terminal; and

a fourth transistor connected in series to the third transistor,

wherein an intermediate node between the first transistor and the second transistor of one differential pair circuit is connected to a control terminal of the fourth transistor in the differential pair circuit that outputs one of the first non-inverted signal or the first inverted signal, and

an intermediate node between the third transistor and the fourth transistor of the second differential pair is connected to a control terminal of the second transistor in the differential pair circuit that outputs the other of the first non-inverted signal and the first inverted signal.

6. The signal conversion circuit according to claim 1 , further comprising:

a first inverter group for inverting the first non-inverted signal for an even number of times and inputting the first non-inverted signal to the interpolation circuit; and

a second inverter group for inverting the first inverted signal for an even number of times and inputting the inverted signal to the first inverter.

7. A signal conversion circuit comprising:

a conversion unit for converting a differential signal being inputted into a first single-ended signal and a second single-ended signal, said first single-ended signal having a duty ratio larger by an error compared to a duty ratio of said inputted differential signal and a said second single-ended signal having a duty ratio smaller by an error compared to said duty ratio of said inputted differential signal; and

an interpolation unit for interpolating the first single-ended signal and the second single-ended signal.

8. The signal conversion circuit according to claim 7 , wherein the first and the second single-ended signals are non-inverted signals which are the amplified differential signal.

9. The signal conversion circuit according to claim 8 , wherein the conversion unit comprises:

a first inverter group for inverting the amplified differential signal for an even number of times and transferring the amplified differential signal as the first single-ended signal; and

a second inverter group for inverting the amplified differential signal for an odd number of times and transferring the amplified differential signal as the second single-ended signal.

10. The signal conversion circuit according to claim 8 , wherein the conversion unit comprises a first differential pair transistor for amplifying the differential signal and the first and the second single-ended signals are generated according to a differential signal amplified by the first differential pair transistor.

11. The signal conversion circuit according to claim 8 , wherein:

the conversion unit comprises a first and a second differential pair transistors for amplifying the differential signal;

the first single-ended signal is generated according to a signal that is a differential signal amplified by the first differential pair transistor; and

the second single-ended signal is generated according to a signal that is a differential signal amplified by the second differential pair transistor.

12. The signal conversion circuit according to claim 7 , wherein:

the interpolation unit sets a waveform that lies almost midway between a rising waveform of the first single-ended signal and a rising waveform of the second single-ended signal to be a rising waveform for an output signal, and

a waveform that lies almost midway between a falling waveform of the first single-ended signal and a falling waveform of the second single-ended signal to be a falling waveform for an output signal.

13. A signal conversion circuit for converting an inputted differential signal into a single-ended signal, comprising:

a differential amplifier circuit for amplifying the differential signal, and generating a first non-inverted signal and a first inverted signal being inverted the first non-inverted signal;

a first inverter for generating a second non-inverted signal being inverted the first inverted signal; and

an interpolation unit for interpolating a phase difference between the first non-inverted signal and the second non-inverted signal, wherein the interpolation circuit comprises:

a first and a second interpolation transistors for inputting the first non-inverted signal to a control terminal;

a third and a fourth interpolation transistors for inputting the second non-inverted signal to a control terminal;

a first parallel circuit including the first interpolation transistor and the third interpolation transistor connected in parallel to the first transistor;

a second parallel circuit including the second interpolation transistor and the fourth interpolation transistor connected in parallel to the second transistor, and connected in series with the first parallel circuit; and

a capacitor connected to an intermediate node between the first parallel circuit and the second parallel circuit.

Assignments (3)
CHANGE OF ADDRESS Recorded Nov 29, 2017
From: RENESAS ELECTRONICS CORPORATION
To: RENESAS ELECTRONICS CORPORATION
Reel/Frame 044928/0001 →
CHANGE OF NAME Recorded Nov 4, 2010
From: NEC ELECTRONICS CORPORATION
To: RENESAS ELECTRONICS CORPORATION
Reel/Frame 025311/0833 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 31, 2006
From: WATANABE, MASAFUMI
To: NEC ELECTRONICS CORPORATION
Reel/Frame 017938/0496 →