IP Library Granted Patent US 7,851,275
Granted Patent B2
US 7,851,275 · App. 11/444,394 · Granted Dec 14, 2010

Pixel of image sensor and method for fabricating the same

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Quick Facts
Patent No.
US 7,851,275
App. No.
11/444,394
Granted
Dec 14, 2010
Kind
B2
Abstract

A pixel of an image sensor includes a polysilicon layer, and an active region which needs to be electrically coupled with the polysilicon layer, wherein the polysilicon layer extends over a portion of the active region, such that the polysilicon layer and the active region are partially overlapped, and the polysilicon layer and the active region are coupled through a buried contact structure.

Claims (28)

1. A method for fabricating a pixel of an image sensor, wherein the pixel comprises a floating diffusion region configured to receive photocharges from a photodetector of the pixel, a MOS drive transistor having a gate and configured as a source follower, and a MOS reset transistor having a drain, the method comprising:

depositing an isolating field oxide about a peripheral portion of an area of a substrate to define an active region in the substrate;

forming a lightly doped diffusion region in the active region of the substrate;

forming a gate oxide layer over the active region, wherein the gate oxide layer further extends over a gate region of the MOS drive transistor;

forming a first polysilicon layer over the gate oxide layer in the active region, wherein the first polysilicon layer further extends over the gate oxide layer of the gate region of the MOS drive transistor;

forming a contact mask over the first polysilicon layer in the active region, wherein the contact mask leaves at least a portion of the first polysilicon layer exposed as an unmasked region;

performing an ion-implantation process to direct ions through the first polysilicon layer and into the gate oxide layer to break down the gate oxide layer in the unmasked region to render the gate oxide layer in the unmasked region conductive thereby providing an electrically conductive path between the first polysilicon layer and the lightly doped diffusion region;

removing the contact mask;

forming a second polysilicon layer over the first polysilicon layer;

performing gate masking and etching processes to pattern the first and second polysilicon layers, wherein the first and second polysilicon layers are patterned to form the gate of the MOS drive transistor, and wherein the first and second polysilicon layers are patterned to provide a conductive path between the broken-down gate oxide layer in the active region and either the gate of the MOS drive transistor or drain of the reset transistor; and

forming a highly doped diffusion region in the active region of the substrate to form the floating diffusion region, wherein the floating gate diffusion region is in contact with the lightly doped diffusion region.

2. The method of claim 1 , wherein the first and second polysilicon layers are masked and etched to provide a conductive path between the broken down gate oxide layer in the active region and the gate of the MOS drive transistor.

3. The method of claim 1 , wherein the first and second polysilicon layers are masked and etched to provide a conductive path between the broken-down gate oxide layer in the active region and the drain of the MOS reset transistor.

4. The method of claim 1 , wherein the first and second polysilicon layers are masked and etched to provide a conductive path between the broken-down gate oxide layer in the active region and both the gate of the MOS drive transistor and the drain of the MOS reset transistor.

5. A method for fabricating a pixel of an image sensor, wherein the pixel comprises a floating gate diffusion region configured to receive photocharges from a photodetector of the pixel, a MOS drive transistor having a gate and configured as a source follower, and a MOS reset transistor having a drain, the method comprising:

depositing an isolating field oxide about a peripheral portion of an area of a substrate to define an active region in the substrate;

forming a lightly doped diffusion region in the active region of substrate;

forming a gate oxide layer over the lightly doped diffusion region of the active region, wherein the gate oxide layer extends over a gate region of the MOS drive transistor;

forming a polysilicon layer over the gate oxide layer in the active region and over the gate oxide in the gate region of the MOS drive transistor;

forming a contact mask over the polysilicon layer in the active region, wherein the contact mask leaves at least a portion of the polysilicon layer exposed to form an unmasked region;

etching the polysilicon layer to reduce the thickness of the polysilicon layer in the unmasked region;

performing an ion-implantation process to direct ions through the polysilicon layer and into the gate oxide layer in the unmasked region to break down the gate oxide layer to thereby render the gate oxide layer in the unmasked region the gate oxide layer conductive and provide an electrically conductive path between the polysilicon layer and the lightly doped diffusion region;

removing the contact mask;

performing a gate masking and etching process to pattern the polysilicon layer, wherein the polysilicon layer is patterned to form the gate of the MOS drive transistor, and wherein the polysilicon layer is further patterned to provide a conductive path between the broken-down gate oxide layer in the active region and either the gate of the MOS drive transistor or the drain of the MOS reset transistor; and

forming a highly doped diffusion region in the active region of substrate, wherein the highly doped diffusion region is in contact with the lightly doped diffusion region, and wherein the highly doped diffusion region forms the floating gate diffusion region of the pixel.

6. The method of claim 5 , wherein the polysilicon layer is masked and etched to provide a conductive path between the broken-down gate oxide layer in the active region and the gate of the MOS drive transistor.

7. The method of claim 5 , wherein the polysilicon layer is masked and etched to provide a conductive path between the broken down gate oxide layer in the active region and the drain of the MOS reset transistor.

8. The method of claim 5 , wherein the polysilicon layer is masked and etched to provide a conductive path between the broken-down gate oxide layer in the active region and both the gate of the MOS drive transistor and the drain of the MOS reset transistor.

Assignments (5)
MERGER Recorded Jul 22, 2011
From: CROSSTEK CAPITAL, LLC
To: INTELLECTUAL VENTURES II LLC
Reel/Frame 026637/0632 →
PARTIAL RELEASE OF SECURITY INTEREST Recorded Aug 10, 2009
From: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL TRUSTEE
To: MAGNACHIP SEMICONDUCTOR, LTD.
Reel/Frame 023075/0054 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 30, 2009
From: MAGNACHIP SEMICONDUCTOR, LTD.
To: CROSSTEK CAPITAL, LLC
Reel/Frame 022764/0270 →
AFTER-ACQUIRED INTELLECTUAL PROPERTY KUN-PLEDGE AGREEMENT Recorded Feb 18, 2009
From: MAGNACHIP SEMICONDUCTOR, LTD.
To: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL TRUSTEE
Reel/Frame 022277/0133 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 1, 2006
From: CHOI, WOON-IL; KIM, HYUNG-SIK; KIM, UI-SIK
To: MAGNACHIP SEMICONDUCTOR, LTD.
Reel/Frame 017959/0553 →