Thin film transistor array panel and method for manufacturing the same
The present invention provides a thin film transistor array panel comprising a substrate; a gate line containing Ag formed on the substrate at a low temperature to prevent agglomeration, a first gate insulating layer formed on the gate line, a second gate insulating layer formed on the first gate insulating layer, a data line perpendicularly intersecting the gate line, and a thin film transistor connected to the gate line and the data line, and a manufacturing method thereof.
1 . A thin film transistor array panel comprising:
a substrate;
a gate line containing Ag formed on the substrate;
a gate insulating layer formed at a temperature lower than 280° C. on the gate line;
a data line perpendicularly intersecting the gate line; and
a thin film transistor connected to the gate line and the data line.
2 . The thin film transistor array panel of claim 1 , wherein the gate insulating layer is deposited at a temperature of 180 to 280° C.
3 . The thin film transistor array panel of claim 1 , wherein the gate line comprises a first conductive layer containing Ag and a second conductive layer containing a conductive oxide.
4 . The thin film transistor array panel of claim 3 , wherein the conductive oxide is ITO or IZO.
5 . A manufacturing method of a thin film transistor array panel comprising:
forming a gate line containing Ag on a substrate;
forming a gate insulating layer at a temperature lower than 280° C. on the gate line;
forming a semiconductor layer on the gate insulating layer;
forming a data line and a drain electrode on the gate insulating layer and the semiconductor layer; and
forming a pixel electrode connected to the drain electrode.
6 . The method of claim 5 , wherein the formation of the gate insulating layer comprises deposition performed at a temperature of 180 to 280° C.
7 . The method of claim 5 , wherein the formation of the gate insulating layer comprises applying at least one selected from among silane gas (SiH 4 ), hydrogen gas (H 2 ), and helium gas (He).
8 . The method of claim 7 , wherein the flow ratio of the silane gas (SiH 4 ) and the hydrogen gas (H 2 ) or the flow ratio of the silane gas (SiH 4 ) and the helium gas (He) is between 5 and 20.
9 . The method of claim 5 , wherein the formation of the data line and the drain electrode comprises deposition performed at a temperature of 180 to 280° C.
10 . A thin film transistor array panel comprising:
a substrate;
a gate line containing Ag formed on the substrate;
a first gate insulating layer formed on the gate line;
a second gate insulating layer formed on the first gate insulating layer;
a data line perpendicularly intersecting the gate line; and
a thin film transistor connected to the gate line and the data line.
11 . The thin film transistor array panel of claim 10 , wherein the first gate insulating layer is formed at a temperature lower than that of the second insulating layer.
12 . The thin film transistor array panel of claim 10 or 11 , wherein the first gate insulating layer is formed at a temperature of 130 to 280° C.
13 . The thin film transistor array panel of claim 10 , wherein the first gate insulating layer has a thickness of 100 to 500 Å.
14 . The thin film transistor array panel of claim 10 , wherein the first gate insulating layer comprises silicon nitride or silicon oxide.
15 . The thin film transistor array panel of claim 10 , wherein the gate line comprises a first conductive layer containing Ag and a second conductive layer containing a conductive oxide.
16 . The thin film transistor array panel of claim 15 , wherein the conductive oxide is ITO or IZO.
17 . A manufacturing method of a thin film transistor array panel, comprising:
forming a gate line containing Ag on a substrate;
forming a first gate insulating layer on the gate line;
forming a second gate insulating layer and a semiconductor layer at a higher temperature than the formation of the first gate insulating layer on the first gate insulating layer;
forming a data line and a drain electrode on the second gate insulating layer and the semiconductor layer; and
forming a pixel electrode connected to the drain electrode.
18 . The method of claim 17 , wherein the formation of the first gate insulating layer is performed at a temperature of 130 to 280° C.
19 . The method of claim 17 , wherein the formation of the gate line comprises a step of forming a conductive layer containing a conductive oxide and a step of forming a conductive layer containing Ag.
20 . The method of claim 17 , wherein the formation of the data line and the drain electrode comprises deposition performed at a temperature of 180 to 280° C.