Microelectronic element chips
View Patent ↗Apparatus including a chip substrate having a first chip surface facing away from a second chip surface; an array of microelectronic elements on the first chip surface; and an array of conductors each in communication with one of the microelectronic elements, the conductors passing through the chip substrate and fully spanning a distance between the first and second chip surfaces. Process including: providing an apparatus including a chip substrate having a first chip surface facing away from a second chip surface, an array of microelectronic elements being on the first chip surface, an array of conductors each being in communication with one of the microelectronic elements and partially spanning an average distance between the first and second chip surfaces; bonding a temporary support carrier onto the array of microelectronic elements; removing a portion of the chip substrate, thereby reducing the average distance between the first and second chip surfaces; and forming an under bump metallization pad at the second chip surface in electrical communication with a conductor.
1. An apparatus, comprising:
a chip substrate having a first chip surface facing away from a second chip surface;
an array of microelectronic elements on the first chip surface, each of the microelectronic
elements being a member of at least one of the following classes: semiconductor devices,
passive filters, sensors, and optoelectronic devices; and
an array of conductors each in communication with one of the microelectronic elements, each of the conductors passing from a first point on the chip surface at the one of the microelectronic elements, entirely within the chip substrate to a second point on the second chip surface at an under bump metallization pad, wherein the distance within the chip substrate between the first and second points is less than about 150 micrometers.
2. The apparatus of claim 1 , including a barrier layer on the second chip surface, wherein the an under bump metallization pad passes through the barrier layer.
3. The apparatus of claim 2 , including an insulating layer on the barrier layer ,wherein the under bump metallization pads are mutually separated by the insulating layer.
4. The apparatus of claim 2 , including lateral wires on the barrier layer transforming a first conductor array into a second conductor array.
5. The apparatus of claim 1 , including a solder bump in electrical communication with the under bump metallization pad.
6. The apparatus of claim 1 , including a temporary support carrier having a first carrier surface bonded onto the array of microelectronic elements.
7. The apparatus of claim 6 , in which the temporary support carrier includes a second carrier surface facing away from the first carrier surface, and a plurality of perforations that reach from the first carrier surface to the second carrier surface.
8. The apparatus of claim 1 , in which the under bump metallization pad is bonded to and in electrical communication with a second substrate.
9. The apparatus of claim 1 , in which the distance is less than about 100micrometers.
10. The apparatus of claim 1 , wherein the semiconductor device utilizes a doped semiconductor p-n hetero-junction between Group 3-5, 2-6, or 4-4semiconductors that allows a controlled flow across the hetero-junction of electrons, holes, or both electrons and holes.
11. The apparatus of claim 1 , wherein the semiconductor device is a transistor or diode.
12. The apparatus of claim 1 , wherein the optoelectronic device includes a micro-electro-mechanical system.
13. The apparatus of claim 12 , wherein the micro-electro-mechanical system includes sensors.
14. The apparatus of claim 12 , wherein the micro-electro-mechanical system includes optical elements.