IP Library Granted Patent US 7,688,054
Granted Patent B2
US 7,688,054 · App. 11/446,036 · Granted Mar 30, 2010

Bandgap circuit with temperature correction

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Quick Facts
Patent No.
US 7,688,054
App. No.
11/446,036
Granted
Mar 30, 2010
Kind
B2
Abstract

A temperature corrected voltage bandgap circuit is provided. The circuit includes first and second diode connected transistors. A first switched current source is coupled to the one transistor to inject or remove a first current into or from the emitter of that transistor. The first current is selected to correct for curvature in the output voltage of the bandgap circuit at one of hotter or colder temperatures.

Claims (49)

1. A bandgap circuit, comprising:

a diode-connected first transistor and a diode-connected second transistor, wherein the first and second transistors each have a plurality of terminals and are connected in a bandgap circuit; and

a first switchable current source including a third transistor having a plurality of terminals, wherein at least two of the plurality of terminals are connected to the second transistor, and wherein the first switchable current source is configured to inject a first predetermined current into the second transistor when a voltage between two of the second transistor terminals has a predetermined relationship to a first voltage, whereby a first temperature compensation is provided to the bandgap circuit.

2. The bandgap circuit of claim 1 , wherein one of the first or second transistors has an area that is a multiple, A, times the area of the other of the first or second transistors.

3. The bandgap circuit of claim 1 , further comprising a single substrate including the first and second transistors, wherein the first switchable current source is formed on the substrate.

4. The bandgap circuit of claim 3 , wherein both the first and second transistors are bipolar transistors.

5. The bandgap circuit of claim 4 , wherein the first switchable current source comprises MOS transistors.

6. The bandgap circuit of claim 3 , wherein the substrate is of a type utilizing CMOS N-well process technology.

7. The bandgap circuit of claim 6 , wherein both the first and second transistors comprise a substrate PNP transistor.

8. The bandgap circuit of claim 7 , wherein the first switchable current source comprises CMOS transistors.

9. The bandgap circuit of claim 1 , further comprising a second switchable current source coupled to the first transistor and configured to remove a second predetermined current from the first transistor when the voltage between two of the first transistor terminals has a predetermined relationship to a second voltage, whereby a second temperature compensation is provided to the bandgap circuit.

10. The bandgap circuit of claim 9 , wherein:

one of the first or second transistors has an area that is a multiple, A, times the area of the other of the first or second transistors;

the first temperature compensation compensates for effects of temperatures above a first predetermined temperature of the substrate; and

the second temperature compensation compensates for effects of temperatures below a second predetermined temperature of the substrate.

11. The bandgap circuit of claim 9 , further comprising a single substrate including the first and second transistors, wherein the first and second switchable current sources are formed on the substrate.

12. The bandgap circuit of claim 11 , wherein both the first and second transistors are bipolar transistors.

13. The bandgap circuit of claim 12 , wherein both the first and second switchable current sources comprise MOS transistors.

14. The bandgap circuit of claim 11 , wherein the substrate is of a type utilizing CMOS N-well process technology.

15. The bandgap circuit of claim 14 , wherein both the first and second transistors comprise a substrate PNP transistor.

16. The bandgap circuit of claim 15 , wherein both the first and second switchable current sources comprise CMOS transistors.

17. A temperature corrected bandgap circuit, comprising:

a first transistor and a second transistor, wherein the area of the first transistor is selected to be a predetermined multiple of the area of the second transistor;

first and second serially-connected resistors connected between an output node and the emitter of the first transistor;

a first node disposed between the first and second serially-connected resistors;

a third resistor connected in series between the output node and the emitter of the second transistor;

a second node disposed between the third resistor and the second transistor emitter;

a third node disposed between the emitter of the first transistor and the first and second serially-connected resistors;

a differential input amplifier having a first input coupled to the first node and a second input coupled to the second node, wherein the amplifier has its output coupled to the output node; and

a first switched current source including a first voltage responsive switch comprising a third transistor having a plurality of terminals, wherein at least two of the plurality of terminals are coupled to the third node, wherein the first voltage responsive switch is configured to inject or remove a first current into or from the first transistor when an output voltage at the output node is at a first predetermined level, and wherein the first current is selected to provide temperature correction in the output voltage for one of hotter or colder temperatures.

18. The bandgap circuit of claim 17 , further comprising a second switched current source including a second voltage responsive switch coupled to the second transistor and configured to remove or inject a second current from or into the second transistor when the output voltage at the output node is at a second predetermined level, wherein the second current is selected to provide temperature correction in the output voltage for the other of the hotter or colder temperatures.

19. The bandgap circuit of claim 18 , wherein both the first and second transistors are bipolar transistors.

20. The bandgap circuit of claim 19 , wherein both the first and second switched current sources and comprise MOS transistors.

21. The bandgap circuit of claim 20 , wherein:

the bandgap circuit is formed on a single substrate; and

the substrate is of a type utilizing CMOS N-well process technology.

22. The bandgap circuit of claim 17 , wherein the first and second transistors are bipolar transistors.

23. The bandgap circuit of claim 22 , wherein the first switched current source comprises MOS transistors.

24. The bandgap circuit of claim 23 , wherein:

the bandgap circuit is formed on a single substrate; and

the substrate is of a type utilizing CMOS N-well process technology.

25. The bandgap circuit of claim 17 , wherein the first voltage responsive switch comprises only three transistors.

26. A bandgap circuit, comprising:

a diode-connected first transistor and a diode-connected second transistor, wherein the first and second transistors each have a plurality of terminals and are connected in a bandgap circuit; and

a first switchable current source including a third transistor having a plurality of terminals, wherein at least two of the plurality of terminals are coupled to the second transistor, and wherein the first switchable current source is configured to remove a first predetermined current from the second transistor when a voltage between two of the second transistor terminals has a predetermined relationship to a first voltage, whereby a first temperature compensation is provided to the bandgap circuit.

27. A bandgap circuit, comprising:

a diode-connected first transistor and a diode-connected second transistor, wherein the first and second transistors each have a plurality of terminals and are connected in a bandgap circuit;

a first switchable current source including a third transistor having a plurality of terminals, wherein at least two of the plurality of terminals are coupled to the second transistor, and wherein the first switchable current source is configured to inject a first predetermined current into the second transistor when a voltage between two of the second transistor terminals has a predetermined relationship to a first voltage, whereby a first temperature compensation is provided to the bandgap circuit; and

a second switchable current source coupled to the first transistor and configured to remove a second predetermined current from the first transistor when the voltage between two of the first transistor terminals has a predetermined relationship to a second voltage, whereby a second temperature compensation is provided to the bandgap circuit.

Assignments (7)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 15, 2008
From: ANDIGILOG, INC.
To: DOLPAN AUDIO, LLC
Reel/Frame 021687/0437 →
RELEASE OF SECURITY INTEREST Recorded Jun 23, 2008
From: VALLEY VENTURES III, L.P.; MISSION VENTURES II, L.P.; MISSION VENTURES AFFILIATES II, L.P.; PALISADES VENTURES, L.P.; PALISADES QUALIFIED INVESTORS, L.P.; PALISADES NON-QUALIFIED INVESTORS, L.P.; OM ANDIGILOG INVESTORS II, LLC; VENTURE LENDING & LEASING IV, LLC; LIEPOLD, CARL F
To: ANDIGILOG, INC.
Reel/Frame 021127/0792 →
RELEASE OF SECURITY INTEREST Recorded May 21, 2008
From: VALLEY VENTURES III, L.P.; MISSION VENTURES II, L.P.; MISSION VENTURES AFFILIATES II, L.P.; PALISADES VENTURES, L.P.; PALISADES QUALIFIED INVESTORS, L.P.; PALISADES NON-QUALIFIED INVESTORS, L.P.; OM ANDIGILOG INVESTORS II, LLC
To: ANDIGILOG, INC.
Reel/Frame 020976/0327 →
SECURITY AGREEMENT Recorded Mar 13, 2008
From: ANDIGILOG, INC.
To: VALLEY VENTURES III, L.P.; VALLEY VENTURES III ANNEX, L.P.; MISSION VENTURES II, L.P.; MISSION VENTURES AFFILIATES II, L.P.; INLIGN CP IV, LLC; DINES TRUST, DATED 12/99; GORDON, MARK; BONHAM, ALEX
Reel/Frame 020645/0218 →
SECURITY AGREEMENT Recorded Nov 7, 2006
From: ANDIGILOG, INC.
To: VALLEY VENTURES III, L.P.; MISSION VENTURES II, L.P.; MISSION VENTURES AFFILIATES II, L.P.; PALISADES VENTURES, L.P.; PALISADES QUALIFIED INVESTORS, L.P.; PALISADES NON-QUALIFIED INVESTORS, L.P.; OM ANDIGILOG INVESTORS II, LLC; VENTURE LENDING & LEASING IV, LLC; LIEPOLD, CARL F
Reel/Frame 018490/0055 →
SECURITY AGREEMENT Recorded Jul 26, 2006
From: ANDIGILOG, INC.
To: VALLEY VENTURES III, L.P.; MISSION VENTURES II, L.P.; MISSION VENTURES AFFILIATES II, L.P.; PALISADES VENTURES, L.P.; PALISADES QUALIFIED INVESTORS, L.P.; PALISADES NON-QUALIFIED INVESTORS, L.P.; OM ANDIGILOG INVESTORS II, LLC
Reel/Frame 017996/0519 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 2, 2006
From: CAVE, DAVID
To: ANDIGILOG, INC.
Reel/Frame 017944/0229 →