Method and system for generating prefetch information for multi-block indirect memory access chains

1. A method, comprising:

selecting a particular one of one or more chains of indirect memory accesses corresponding to a procedure, wherein each of said one or more chains comprises at least a respective head memory access that does not depend for its memory address computation on another prefetch candidate memory access within said procedure and one or more indirect memory accesses that depend for their respective memory address computations either directly or indirectly on said respective head memory access;

determining a prefetch-ahead value for said particular chain;

generating a load operation corresponding to said head memory access of said particular chain that specifies a target memory address that is dependent upon both said prefetch-ahead value and a memory address of said head memory access; and

for a terminal indirect memory access included in said particular chain, generating a respective prefetch operation that is dependent for its memory address computation on results of one or more preceding generated load operations in the same manner as its corresponding terminal indirect memory access depends upon one or more preceding memory accesses in said particular chain.

2. The method as recited in claim 1 , wherein said particular chain includes at least one non-terminal memory access other than said head memory access, and wherein the method further comprises:

for each non-terminal indirect memory access included in said particular chain, generating a respective load operation that is dependent for its memory address computation on results of one or more preceding generated load operations in the same manner as its corresponding non-terminal indirect memory access depends upon one or more preceding memory accesses in said particular chain.

3. The method as recited in claim 1 , wherein said procedure is an iterative loop procedure.

4. The method as recited in claim 3 , wherein determining said prefetch-ahead value for said particular chain is dependent upon an expected latency of prefetching and an expected latency of iteration of said procedure.

5. The method as recited in claim 3 , further comprising:

determining whether said terminal memory access of said particular chain is used to compute a base address of a memory access in an inner iterative loop of said iterative loop procedure; and

in response to determining that said terminal memory access of said particular chain is used to compute said base address of a memory access in said inner iterative loop, generating one or more additional prefetch operations, wherein a respective memory address of each of said one or more additional prefetch operations is a function of both said memory address of said prefetch operation corresponding to said terminal memory access and a multiple of a cache line size.

6. The method as recited in claim 3 , wherein said particular chain includes N memory accesses indexed from 1 to N beginning with said head memory access, wherein N is an integer greater than 1, and wherein the method further comprises:

determining a total of N−1 prefetch-ahead values for said particular chain, wherein each of said N−1 prefetch-ahead values corresponds to a respective future iteration of said iterative loop procedure; and

generating additional load and prefetch operations dependent from said N−1 prefetch-ahead values such that for said head memory access, load operations corresponding to N−1 future iterations of said iterative loop procedure are generated, and for a given j th memory access of said particular chain other than said head memory access, a combination of load operations and prefetch operations corresponding to N−j+1 future iterations of said iterative loop procedure are generated.

7. The method as recited in claim 1 , wherein at least some run-time faults or exceptions are suppressed for each of said load operations.

8. The method as recited in claim 1 , wherein said respective prefetch operation is implemented as a load operation whose result is not used by another operation within said procedure.

9. The method as recited in claim 1 , wherein selecting said particular chain is dependent upon a degree to which memory accesses included in said particular chain appear in other ones of said one or more chains.

10. The method as recited in claim 1 , further comprising suppressing generation of a second load operation or prefetch operation for any memory access within said procedure for which a load operation or prefetch operation has previously been generated.

11. The method as recited in claim 1 , wherein said head memory access of said particular chain depends for its memory address computation on another memory access within said procedure that is predictably invariant with respect to said procedure.

12. A computer-accessible storage medium storing instructions, wherein the instructions are executable to:

select a particular one of one or more chains of indirect memory accesses corresponding to a procedure, wherein each of said one or more chains comprises at least a respective head memory access that does not depend for its memory address computation on another memory access within said procedure and one or more indirect memory accesses that depend for their respective memory address computations either directly or indirectly on said respective head memory access;

determine a prefetch-ahead value for said particular chain;

generate a load operation corresponding to said head memory access of said particular chain that specifies a target memory address that is dependent upon both said prefetch-ahead value and a memory address of said head memory access; and

for a terminal indirect memory access included in said particular chain, generate a respective prefetch operation that is dependent for its memory address computation on results of one or more preceding generated load operations in the same manner as its corresponding terminal indirect memory access depends upon one or more preceding memory accesses in said particular chain.

13. The computer-accessible storage medium as recited in claim 12 , wherein said particular chain includes at least one non-terminal memory access other than said head memory access, and wherein the instructions are further executable to:

for each non-terminal indirect memory access included in said particular chain, generate a respective load operation that is dependent for its memory address computation on results of one or more preceding generated load operations in the same manner as its corresponding non-terminal indirect memory access depends upon one or more preceding memory accesses in said particular chain.

14. The computer-accessible storage medium as recited in claim 12 , wherein said procedure is an iterative loop procedure.

15. The computer-accessible storage medium as recited in claim 14 , wherein the instructions are further executable to determine said prefetch-ahead value for said particular chain dependent upon an expected latency of prefetching and an expected latency of iteration of said procedure.

16. The computer-accessible storage medium as recited in claim 14 , wherein the instructions are further executable to:

determine whether said terminal memory access of said particular chain is used to compute a base address of a memory access in an inner iterative loop of said iterative loop procedure; and

in response to determining that said terminal memory access of said particular chain is used to compute said base address of a memory access in said inner iterative loop, generate one or more additional prefetch operations, wherein a respective memory address of each of said one or more additional prefetch operations is a function of both said memory address of said prefetch operation corresponding to said terminal memory access and a multiple of a cache line size.

17. The computer-accessible storage medium as recited in claim 14 , wherein said particular chain includes N memory accesses indexed from 1 to N beginning with said head memory access, wherein N is an integer greater than 1, and wherein the instructions are further executable to:

determine a total of N−1 prefetch-ahead values for said particular chain, wherein each of said N−1 prefetch-ahead values corresponds to a respective future iteration of said iterative loop procedure; and

generate additional load and prefetch operations dependent from said N−1 prefetch-ahead values such that for said head memory access, load operations corresponding to N−1 future iterations of said iterative loop procedure are generated, and for a given j th memory access of said particular chain other than said head memory access, a combination of load operations and prefetch operations corresponding to N−j+1 future iterations of said iterative loop procedure are generated.

18. The computer-accessible storage medium as recited in claim 12 , wherein at least some run-time faults or exceptions are suppressed for each of said load operations.

19. The computer-accessible storage medium as recited in claim 12 , wherein said respective prefetch operation is implemented as a load operation whose result is not used by another operation within said procedure.

20. The computer-accessible storage medium as recited in claim 12 , wherein the instructions are further executable to suppress generation of a second load operation or prefetch operation for any memory access within said procedure for which a load operation or prefetch operation has previously been generated.

21. A system, comprising:

a system memory configured to store instructions; and

one or more processors, wherein the instructions are executable by at least one of the one or more processors to:

select a particular one of one or more chains of indirect memory accesses corresponding to a procedure, wherein each of said one or more chains comprises at least a respective head memory access that does not depend for its memory address computation on another memory access within said procedure and one or more indirect memory accesses that depend for their respective memory address computations either directly or indirectly on said respective head memory access;

determine a prefetch-ahead value for said particular chain;

generate a load operation corresponding to said head memory access of said particular chain that specifies a target memory address that is dependent upon both said prefetch-ahead value and a memory address of said head memory access; and

for a terminal indirect memory access included in said particular chain, generate a respective prefetch operation that is dependent for its memory address computation on results of one or more preceding generated load operations in the same manner as its corresponding terminal indirect memory access depends upon one or more preceding memory accesses in said particular chain.

22. The system as recited in claim 21 , wherein said particular chain includes at least one non-terminal memory access other than said head memory access, and wherein the instructions are further executable to:

for each non-terminal indirect memory access included in said particular chain, generate a respective load operation that is dependent for its memory address computation on results of one or more preceding generated load operations in the same manner as its corresponding non-terminal indirect memory access depends upon one or more preceding memory accesses in said particular chain.