Use of a thick oxide device as a cascode for a thin oxide transconductance device in MOSFET technology and its application to a power amplifier design
View Patent ↗A power amplifier power amplifier includes a transconductance stage and a cascode stage. The transconductance stage that is operable to receive an input voltage signal and to produce an output current signal. The transconductance stage includes a first Metal Oxide Silicon (MOS) transistor having a first gate oxide thickness and a first channel length. The cascode stage communicatively couples to the transconductance stage and is operable to receive the output current signal and to produce an output voltage signal based thereupon. The cascode stage includes a second MOS transistor having a second gate oxide thickness and a second channel length.
1. A power amplifier comprising:
a primary transconductance stage that receives an input voltage signal and that produces a primary current output;
a secondary transconductance stage that receives the input voltage signal and that produces a secondary current output that is additive to the primary current output;
wherein each of the primary transconductance stage and the secondary transconductance stage includes:
a first Metal Oxide Silicon (MOS) transistor having a first gate oxide thickness and a first channel length and a second MOS transistor having a second gate oxide thickness and a second channel length coupled in cascode with the first MOS transistor; and
wherein the second gate oxide thickness is substantially thicker than the first gate oxide thickness.
2. The power amplifier of claim 1 , wherein the second gate oxide thickness is approximately twice as thick as the first gate oxide thickness.
3. The power amplifier of claim 2 , wherein:
the second gate oxide thickness is approximately 100 Angstroms; and
the first gate oxide thickness is approximately 50 Angstroms.
4. The power amplifier of claim 1 , wherein the second channel length is substantially longer than the first channel length.
5. The power amplifier of claim 4 , wherein the second channel length is approximately twice as long as the first channel length.
6. The power amplifier of claim 5 , wherein:
the second channel length is approximately 0.35 microns; and
the first channel length is approximately 0.18 microns.
7. The power amplifier of claim 1 , further comprising a signal level detection and bias determination module that is operable to apply a controllable bias voltage to the gate of the first MOS transistor.
8. The power amplifier of claim 1 , further comprising a signal level detection and bias determination module that is operable to apply a controllable bias voltage to the gate of the second MOS transistor.
9. The power amplifier of claim 1 , wherein the primary transconductance stage and the secondary transconductance stage form a first half of a differential power amplifier and a second half of the differential power amplifier includes corresponding components.
10. The power amplifier of claim 1 , wherein the primary transconductance stage and the secondary transconductance stage are operable to be biased at different levels.