Chip scale surface mounted device and process of manufacture
View Patent ↗A chip scale package has a semiconductor MOSFET die which has a top electrode surface covered with a layer of a photosensitive liquid epoxy which is photolithographically patterned to expose portions of the electrode surface and to act as a passivation layer and as a solder mask. A solderable contact layer is then formed over the passivation layer. The individual die are mounted drain side down in a metal clip or can with the drain electrode disposed coplanar with a flange extending from the can bottom.
1. A semiconductor device package comprising:
a power semiconductor device, said power semiconductor device including a first power electrode on one major surface thereof, and a second power electrode on a second opposing major surface thereof;
a passivation layer over said second power electrode of said power semiconductor device;
at least one solderable body over said second power electrode of said power semiconductor device; and
a conductive clip, said conductive clip having a web portion electrically and mechanically connected to said first power electrode of said power semiconductor device and at least one connection surface that faces a same direction as said at least one solderable body.
2. The semiconductor device package of claim 1 , wherein said passivation layer is comprised of an epoxy.
3. The semiconductor device package of claim 1 , wherein said passivation layer acts as a solder resist.
4. The semiconductor device package of claim 1 , wherein said passivation layer acts as a plating resist.
5. The semiconductor device package of claim 1 , further comprising a control electrode on said second opposing major surface, and another solderable body over said control electrode.
6. The semiconductor device package of claim 1 , further comprising a plurality of connection surfaces laterally spaced from said at least one connection surface.
7. The semiconductor device package of claim 1 , further comprising another connection surface disposed opposite said at least one connection surface.
8. The semiconductor device package of claim 1 , wherein said clip is cup-shaped, and said at least one connection surface is disposed on one side thereof.
9. The semiconductor device package of claim 8 , further comprising another connection surface disposed on a side opposite said at least one side.
10. The semiconductor device package of claim 1 , wherein said clip is comprised of copper.
11. The semiconductor device package of claim 1 , wherein said clip is silver-plated.
12. The semiconductor device package of claim 1 , wherein said clip does not include a connection surface on at least one side thereof.
13. The semiconductor device package of claim 1 , wherein said power semiconductor device is a power MOSFET.
14. The semiconductor device package of claim 1 , wherein said power semiconductor device is an IGBT.
15. The semiconductor device package of claim 1 , wherein said power semiconductor device is a diode.
16. The semiconductor device package of claim 1 , wherein said power semiconductor device is a thyristor.
17. The semiconductor device package of claim 1 , further comprising a low stress, high adhesion epoxy disposed around said power semiconductor device.
18. The semiconductor device package of claim 1 , wherein said first power electrode is electrically and mechanically connected to said web portion by a conductive adhesive.
19. The semiconductor device package of claim 1 , wherein said conductive clip is U-shaped.
20. The semiconductor device package of claim 1 , further comprising a mold compound disposed thereon.