CMOS image sensor and method for fabricating the same
View Patent ↗A method for fabricating a CMOS image sensor includes: forming a gate electrode on a pixel region of the semiconductor substrate and, at the same time, forming a polysilicon pattern on a middle resistor region; forming a first lightly doped n-type diffusion region on the photodiode region; forming a second lightly doped n-type diffusion region on the transistor region; consecutively forming first and second insulating layers on the entire surface of the semiconductor substrate; removing a predetermined portion of the second insulation layer on the transistor region and the middle resistor region; forming a third insulation layer on the entire surface of the semiconductor substrate; forming sidewalls of the first insulating layer and the third insulating layer on the gate electrode and the polysilicon pattern by performing an etch-back process; and heavily doping n-type impurities in the transistor region and the polysilicon pattern.
1. A method for fabricating a CMOS (complementary metal oxide silicon) image sensor comprising:
forming a gate electrode on a pixel region of a semiconductor substrate and, at the same time, forming a polysilicon pattern on a middle resistor region of the semiconductor substrate;
forming a first lightly doped n-type diffusion region on a photodiode region of the pixel region;
forming a second lightly doped n-type diffusion region on a transistor region of the pixel region;
consecutively forming a first insulating layer and a second insulating layer on the semiconductor substrate;
removing a predetermined portion of the second insulating layer from the transistor region and the middle resistor region;
forming a third insulating layer on the semiconductor substrate;
forming sidewalls of the first insulating layer and the second insulating layer on the gate electrode and the polysilicon pattern by performing an etch-back process; and
implanting n-type impurities in the transistor region and the polysilicon pattern.
2. The method according to claim 1 , wherein the first insulating layer is an oxide layer or a nitride layer and the second insulating layer is an oxide layer or a nitride layer.
3. The method according to claim 2 , wherein the oxide layer is a thermal oxide layer of a TEOS-based oxide layer.
4. The method according to claim 1 , wherein the third insulating layer is a nitride layer.
5. The method according to claim 1 , wherein removing a first predetermined portion of the second insulating layer removes the second insulating layer such that the second insulating layer covers a portion of the gate electrode.
6. The method according to claim 5 , wherein the sidewalls are formed on one side of the gate electrode and both sides of the polysilicon pattern.
7. The method according to claim 1 , wherein the sidewalls are formed on one side of the gate electrode and both sides of the polysilicon pattern.
8. The method according to claim 1 , further comprising removing the first insulating layer and the second insulating layer from the first lightly doped n-type diffusion region of the photo diode region.
9. A method for fabricating a CMOS (complementary metal oxide silicon) image sensor, comprising:
providing a semiconductor substrate comprising a pixel region having a photodiode region and a transistor region, and a middle resistor region;
forming a gate electrode on the pixel region and, at the same time, forming a polysilicon pattern on the middle resistor region;
forming a lightly doped n-type diffusion region on the photodiode region;
consecutively forming a first insulating layer and a second insulating layer on the semiconductor substrate;
removing a predetermined portion of the second insulating layer;
forming a third insulating layer on the resulting structure; and
forming sidewalls on the gate electrode and the polysilicon pattern through an etching process.
10. The method according to claim 9 , wherein removing a predetermined portion of the second insulating layer removes the second insulating layer that covers one side of the gate electrode and the middle resistor region.
11. The method according to claim 9 , wherein the sidewalls are formed on one side of the gate electrode and both sides of the polysilicon pattern.
12. The method according to claim 9 , wherein removing a predetermined portion of the second insulating layer removes the second insulating layer that covers the gate electrode and the middle resistor region.
13. The method according to claim 12 , wherein the sidewalls arc formed on both sides of the gate electrode and both sides of the polysilicon pattern.
14. The method according to claim 9 , wherein the sidewalls are formed by etching the first insulating layer and the third insulating layer.
15. The method according to claim 9 , wherein the first insulating layer is an oxide layer or a nitride layer and second insulating layer is an oxide layer or a nitride layer.
16. The method according to claim 15 , wherein the oxide layer is a thermal oxide layer or a TEOS-based oxide layer.
17. The method according to claim 9 , wherein the third insulating layer is a nitride layer.
18. The method according to claim 9 , further comprising removing the first insulating layer and the second insulating layer from the first lightly doped n-type diffusion region of the photo diode region.