Universal logic gate utilizing nanotechnology
View Patent ↗A universal logic gate apparatus is disclosed, which include a plurality of self-assembling chains of nanoparticles having a plurality of resistive connections, wherein the plurality of self-assembling chains of nanoparticles comprise resistive connects utilized to create a universal, reconfigurable logic gate A plasticity mechanism is also provided, which is based on a plasticity rule for creating stable connections from the plurality of self-assembling chains of nanoparticles for use with the universal, reconfigurable logic gate. The plasticity mechanism can be based, for example, on a 2-dimensional binary input data stream, depending upon design considerations. A circuit is also associated with the plurality of self-assembling chains of nanoparticles, wherein the circuit provides a logic bypass that implements a flip-cycle for second-level logic. Additionally, an extractor logic gate is associated with the plurality of self-assembling chains of nanoparticles, wherein the extractor logic gate provides logic functionalities.
1. A universal logic gate apparatus, comprising:
a plurality of self-assembling chains of nanoparticles having a plurality of resistive connections, wherein said plurality of self-assembling chains of nanoparticles comprise resistive connects utilized to create a universal, reconfigurable logic gate thereof; and
a plasticity mechanism based on a plasticity rule for creating stable connections from said plurality of self-assembling chains of nanoparticles for use with said universal, reconfigurable logic gate, wherein said plasticity mechanism is based on an input data stream, wherein said plasticity rule comprises a reproducible modification of a connection resistance in response to input and output electrode activity.
2. The apparatus of claim 1 wherein said input data stream comprises a 2-dimensional binary input data stream.
3. The apparatus of claim 2 further comprising a circuit associated with said plurality of self-assembling chains of nanoparticles, wherein said circuit provides a logic bypass that implements a flip-cycle for second-level logic.
4. The apparatus of claim 2 further comprising at least one extractor logic gate associated with said plurality of self-assembling chains of nanoparticles, wherein said at least one extractor logic gate provides logic functionalities.
5. The apparatus of claim 2 further comprising:
a circuit associated with said plurality of self-assembling chains of nanoparticles, wherein said circuit provides a logic bypass that implements a flip-cycle for second-level logic; and
at least one extractor logic gate associated with said plurality of self-assembling chains of nanoparticles, wherein said at least one extractor logic gate provides logic functionalities.
6. The apparatus of claim 1 wherein said plurality of self-assembling chains of nanoparticles are arranged utilizing dielectrophoresis (DEP).
7. The apparatus of claim 6 wherein said DEP comprises a positive DEP.
8. The apparatus of claim 6 wherein said DEP comprises a negative DEP.