Thin film transistor panel for liquid crystal display and liquid crystal display comprising the same
A thin film transistor substrate for a liquid crystal display, which can provide a required pixel discharging time, and a liquid crystal display comprising the same are disclosed. The thin film transistor substrate comprises a plurality of unit pixels arranged in an (m×n) matrix array, gate lines disposed one by one for every two unit pixels neighboring in a column direction, wherein one gate signal is simultaneously supplied to the two unit pixels via one gate line, data lines intersecting the gate lines, supplying data signals to the unit pixels in synchronization with the gate signals supplied via the gate lines wherein said data lines are arranged two by two between the unit pixels neighboring in a row direction and a thin film transistor TFT formed at each crossing portion of the gate lines and the data lines and transmitting the data signals to pixel electrodes in response to the gate signals.
1 . A thin film transistor substrate for a liquid crystal display panel, comprising:
a plurality of unit pixels arranged in an (m×n) matrix array;
gate lines disposed one for every two unit pixels neighboring in a column direction, wherein one gate signal is simultaneously supplied to the two unit pixels via one gate line;
data lines intersecting the gate lines and supplying data signals to the unit pixels in synchronization with the gate signals supplied via said gate lines wherein said data lines are arranged two between the unit pixels neighboring in a row direction; and
a thin film transistor TFT formed at each crossing portion of the gate lines and the data lines and transmitting the data signals to pixel electrodes in response to the gate signals.
2 . The thin film transistor substrate of claim 1 , wherein when the number of unit pixels in the column direction is n, the number of gate lines is n/2.
3 . The thin film transistor substrate of claim 1 , wherein when the number of unit pixels in the row direction is m, the number of data lines is 2m.
4 . The thin film transistor substrate of claim 1 , wherein each of the data lines is arranged one by one at both sides of unit pixels in the row direction.
5 . The thin film transistor substrate of claim 1 , wherein when the number of unit pixels in the row direction is m, a 2m number of thin film transistors are formed on the gate lines.
6 . The thin film transistor of claim 1 , wherein the gate lines sequentially supply gate signals to the entire gate lines.
7 . A liquid crystal display, comprising:
a source driver for applying a data signal to data lines;
a gate driver for applying a gate signal to gate lines; and
a liquid crystal panel for displaying data through unit pixels in response to the gate signal and the data signal,
the liquid crystal panel comprising:
a plurality of unit pixels arranged in an (m×n) matrix array;
gate lines disposed one for every two unit pixels neighboring in a column direction and simultaneously supplying gate signals;
data lines intersecting the gate lines, supplying data signals to the unit pixels in synchronization with the gate signals supplied via said gate lines wherein said data lines are arranged two between the unit pixels neighboring in a row direction; and
a thin film transistor TFT formed at each crossing portion of the gate lines and the data lines and transmitting the data signals to pixel electrodes in response to the gate signals.
8 . The liquid crystal display of claim 7 , wherein when the number of unit pixels in the column direction is n, the number of gate lines is n/2.
9 . The liquid crystal display of claim 7 , wherein when the number of unit pixels in the row direction is m, the number of data lines is 2m.
10 . The liquid crystal display of claim 7 , wherein each of the data lines is arranged one by one at both sides of unit pixels in the row direction.
11 . The liquid crystal display of claim 7 , wherein when the number of unit pixels in the row direction is m, a 2m number of thin film transistors are formed on the gate lines.
12 . The liquid crystal display of claim 6 , wherein the gate lines sequentially supply gate signals to the entire gate lines.
13 . A method of manufacturing a thin film transistor substrate for a liquid crystal display panel, comprising:
forming a plurality of unit pixels arranged in an (m×n) matrix array;
forming gate lines disposed one for every two unit pixels neighboring in a column direction, wherein one gate signal is simultaneously supplied to the two unit pixels via one gate line;
forming data lines intersecting the gate lines and supplying data signals to the unit pixels in synchronization with the gate signals supplied via said gate lines wherein said data lines are arranged two between the unit pixels neighboring in a row direction; and
forming a thin film transistor TFT formed at each crossing portion of the gate lines and the data lines and transmitting the data signals to pixel electrodes in response to the gate signals.