Array substrate for liquid crystal display device and method of fabricating the same

1. An array substrate for a liquid crystal display device, comprising:

a gate line and a first storage electrode on a substrate, wherein the first storage electrode occupies a portion of the gate line;

a gate insulating layer on the gate line and the first storage electrode;

a data line over the gate insulating layer, the data line crossing the gate line to define a pixel region;

a thin film transistor having a gate electrode connected to the gate line, a semiconductor layer over the gate electrode, a source electrode connected to the data line, and a drain electrode spaced apart from the source electrode;

a passivation layer on the data line, wherein a first thickness of the passivation layer plus the gate insulating layer over the first storage electrode is thinner than a second thickness of the passivation layer plus the gate insulating layer over the gate electrode; and

a pixel electrode and a second storage electrode on the passivation layer, the second storage electrode extended from the pixel electrode and overlapped with the first storage electrode.

2. The array substrate according to claim 1 , wherein the passivation layer has a drain contact hole that exposes a portion of the drain electrode.

3. The array substrate according to claim 2 , wherein the pixel electrode is connected to the drain electrode via the drain contact hole.

4. The array substrate according to claim 1 , wherein the passivation layer has an open portion that exposes the gate insulating layer overlapping the gate line.

5. An array substrate for a liquid crystal display device, comprising:

a gate line on a substrate;

a data line crossing the gate line;

a thin film transistor connected to the gate line and the data line;

a pixel electrode connected to the thin film transistor, the pixel electrode overlapping the gate line in an overlapped region; and

an insulating layer consisting of inorganic material between the gate line and the pixel electrode, wherein a first uniform thickness of the insulating layer corresponding to the overlapped region is thinner than a second thickness of the insulating layer corresponding to regions other than the overlapped region, and wherein in the overlapped region, the gate line, the insulating layer and the pixel electrode form a storage capacitor

and wherein the storage capacitor includes a first storage electrode occupying a portion of the gate line and a second storage electrode extended from the pixel electrode.

6. The array substrate according to claim 5 , wherein the thin film transistor includes a gate electrode connected to the gate line, a semiconductor layer over the gate electrode, a source electrode connected to the data line, and a drain electrode spaced apart from the source electrode.

7. The array substrate according to claim 6 , wherein the insulating layer includes a gate insulating layer between the gate line and the data line and a passivation layer between the thin film transistor and the pixel electrode.

8. The array substrate according to claim 7 , wherein the passivation layer has a drain contact hole that exposes a portion of the drain electrode.

9. The array substrate according to claim 8 , wherein the pixel electrode is connected to the drain electrode via the drain contact hole.