IP Library Granted Patent US 7,342,443
Granted Patent B2
US 7,342,443 · App. 11/450,347 · Granted Mar 11, 2008

Operational amplifier

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Quick Facts
Patent No.
US 7,342,443
App. No.
11/450,347
Granted
Mar 11, 2008
Kind
B2
Abstract

An operational amplifier for canceling an offset and continuously generating an output signal. The operational amplifier includes a first operational amplification unit and a second operational amplification unit each having at least one electrical characteristic that is substantially the same as one another. One of the operational amplification units performs a canceling operation (holding operation and compensation operation) of the offset voltage while the other operational amplification unit performs a non-canceling operation and generates the output voltage by amplifying an input voltage. Both operational amplification units alternately perform the canceling operation and the non-canceling operation.

Claims (31)

1. An operational amplifier for generating an output voltage by amplifying an input voltage, the operational amplifier comprising;

a first capacitor;

a first operational amplification unit connected to the first capacitor and having a first offset voltage, the first operational amplification unit accumulating charge corresponding to the first offset voltage in the first capacitor and alternately performing a canceling operation, for canceling the first offset voltage with the charge accumulated in the first capacitor, and a non-canceling operation, for generating a first output voltage by amplifying the input voltage;

a second capacitor;

a second operational amplification unit connected to the second capacitor, having substantially the same electrical characteristic as the first operational amplification unit, and having a second offset voltage, the second operational amplification unit accumulating charge corresponding to the second offset voltage in the second capacitor and alternately performing a canceling operation, for canceling the second offset voltage with the charge accumulated in the second capacitor, and a non-canceling operation, for generating a second output voltage by amplifying the input voltage; and

an output selection circuit, connected to the first and second operational amplification units, for alternately selecting the first output voltage and the second output voltage as the output voltage of the operational amplifier;

wherein the second operational amplification unit performs the non-canceling operation when the first operational amplification unit is performing the canceling operation, and the second operational amplification unit performs the canceling operation when the first operational amplification unit is performing the non-canceling operation.

2. The operational amplifier according to claim 1 , wherein the first and second operational amplification units each have substantially the same gain.

3. The operational amplifier according to claim 1 , further comprising:

a first feedback resistor, selectively connected to output terminals of the first and second operational amplification units via the output selection circuit, for use as a feedback resistor when the first and second operational amplification units each perform the canceling operation; and

a second feedback resistor, selectively connected to the output terminals of the first and second operational amplification units via the output selection circuit, for use as a feedback resistor when the first and second operational amplification units each perform the non-canceling operation.

4. The operational amplifier according to claim 3 , wherein the first feedback resistor is smaller in size than the second feedback resistor.

5. The operational amplifier according to claim 1 , further comprising:

a first input resistor for receiving the input voltage;

a second input resistor for receiving the input voltage; and

an input selection circuit, connected to the first input resistor, the second input resistor, and the first and second operational amplification units, for selectively connecting the first input resistor to input terminals of the first and second operational amplification units during the canceling operation and for selectively connecting the second input resistor to the input terminals of the first and second operational amplification units during the non-canceling operation.

6. The operational amplifier according to claim 5 , wherein the first input resistor is smaller in size than the second input resistor.

7. The operational amplifier according to claim 5 , wherein the first and second operational amplification units, the output selection circuit, and the input selection circuit operate in accordance with a control signal.

8. The operational amplifier according to claim 1 , wherein the first and second operational amplification units are each switched from the canceling operation to the non-canceling operation after a predetermined time elapses from when the canceling operation starts to cancel the corresponding offset voltage.

9. The operational amplifier according to claim 1 , wherein the first and second operational amplification units each include:

a first differential input circuit having first and second input terminals for receiving the input voltage, and the first differential input circuit including a first transistor connected to the first input terminal and a second transistor connected to the second input terminal;

a current mirror circuit including a third transistor connected to the first transistor and a fourth transistor connected to the second transistor;

a second differential input circuit connected in parallel to the first differential input circuit and including a fifth transistor connected to the third transistor and a sixth transistor connected to the fourth transistor;

a first switch, connected to gates of the first and second transistors, for selectively connecting the gates of the first and second transistors;

a second switch, connected to a gate of the fifth transistor and to the first input terminal, for selectively connecting the gate of the fifth transistor and the first input terminal; and

a third switch, connected to a gate of the sixth transistor and to the second input terminal, for selectively connecting the gate of the sixth transistor and the second input terminal;

wherein the first and second capacitors are each connected between the gates of the fifth and sixth transistors in each of the first and second operational amplification units.

10. The operational amplifier according to claim 1 , wherein the output selection circuit includes a make before break switch.

11. The operational amplifier according to claim 1 , further comprising:

a capacitor, connected to the output selection circuit, for holding the output voltage;

wherein the output selection circuit includes a break before make switch or a make before break switch.

Assignments (9)
CORRECTIVE ASSIGNMENT TO CORRECT THE 8647899 PREVIOUSLY RECORDED ON REEL 035240 FRAME 0429. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY INTERST. Recorded Nov 3, 2020
From: CYPRESS SEMICONDUCTOR CORPORATION; SPANSION LLC
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 058002/0470 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 14, 2016
From: CYPRESS SEMICONDUCTOR CORPORATION
To: MONTEREY RESEARCH, LLC
Reel/Frame 040911/0238 →
PARTIAL RELEASE OF SECURITY INTEREST IN PATENTS Recorded Aug 11, 2016
From: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
To: CYPRESS SEMICONDUCTOR CORPORATION; SPANSION LLC
Reel/Frame 039708/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 30, 2015
From: SPANSION, LLC
To: CYPRESS SEMICONDUCTOR CORPORATION
Reel/Frame 036037/0001 →
SECURITY INTEREST Recorded Mar 21, 2015
From: CYPRESS SEMICONDUCTOR CORPORATION; SPANSION LLC
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 035240/0429 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 11, 2013
From: FUJITSU SEMICONDUCTOR LIMITED
To: SPANSION LLC
Reel/Frame 031205/0461 →
CHANGE OF NAME Recorded Jul 22, 2010
From: FUJITSU MICROELECTRONICS LIMITED
To: FUJITSU SEMICONDUCTOR LIMITED
Reel/Frame 024982/0245 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 12, 2008
From: FUJITSU LIMITED
To: FUJITSU MICROELECTRONICS LIMITED
Reel/Frame 021998/0645 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 12, 2006
From: NISHIMORI, EIJI
To: FUJITSU LIMITED
Reel/Frame 017968/0123 →