Driving circuit, liquid crystal display device and method of driving the same

1. A driving circuit comprising:

a gate driver; and

a power supply to generate a power supply voltage, the power supply voltage is a high level when power is on and the power supply voltage is a low level when power is off,

wherein the power supply voltage enable and disable the gate driver to be driven,

wherein the gate driver outputs one of a gate driving signal or a discharge signal according to level of the power supply voltage,

wherein the gate driving signal includes a scan signal having a gate high voltage and a gate low voltage,

wherein the discharge signal is a voltage with a level equal to level of the gate high voltage, is generated when the power supply voltage is the low level and is supplied to gate lines of a liquid crystal panel to discharge a residual voltage of the liquid crystal panel,

wherein the gate driver comprises:

a plurality of shift registers, each connecting an output terminal thereof to a corresponding the gate line of the liquid crystal panel,

a plurality of logic controllers, each connecting to an input terminal of a first corresponding shift register to generate a control signal having at least two states and the output terminal of a second corresponding shift register,

wherein each of the logic controllers receive the power supply voltage and one of a gate start pulse signal or an output signal of the previous shift register,

wherein the logic controller generates the control signal with a high level during a predetermined time when the power supply voltage is the low level,

wherein the gate driver outputs the discharge signal when the power supply voltage is the low level and supplies the discharge signal to the gate lines.

2. The driving circuit according to claim 1 , wherein the gate driving signal is output when the power supply voltage is at a high level, and the discharge signal is output when the power supply voltage changes from a high level to a low level.

3. The driving circuit according to claim 1 , wherein each shift register outputs one of the gate driving signal or the discharge signal according to a state of the control signal.

4. The driving circuit according to claim 1 , wherein the first logic controller comprises:

an inverter adapted to receive a start pulse; and

a NAND gate

wherein the inverter output and the supply voltage are input to the NAND gate.

5. The driving circuit according to claim 4 , wherein an output of the first logic controller is determined according to the inverter input voltage when the power supply voltage is supplied.

6. The driving circuit according to claim 4 , wherein the first logic controller maintains a high level output for a time interval when the power supply voltage is shut off.

7. The driving circuit according to claim 1 , wherein the second logic controller comprises:

an inverter connected to an output of a previous shift register and

a NAND gate,

wherein the inverter output and the supply voltage are input to the NAND gate.

8. The driving circuit according to claim 7 , wherein an output state of the second logic controller is determined by the output of the previous shift register when the supply voltage is supplied at a high level.

9. The driving circuit according to claim 7 , wherein the second logic controller maintains a high level state regardless of the output of the previous shift register when the supply voltage is shut off.

10. The driving circuit according to claim 9 , wherein the gate signal maintains a high level voltage during a predetermined time interval after the supply voltage is shut off.

11. The driving circuit according to claim 10 , wherein a voltage of the liquid crystal panel is discharged by the high level gate voltage.

12. The driving circuit according to claim 10 , wherein the predetermined time interval is between the power supply shut off and the gate signal changing to a low level.

13. The driving circuit according to claim 1 , wherein the plurality of logic controller output an output signal of a high level state when the supply voltage is shut off, and the shift register outputs the gate signal voltage according to the logic controller output signal.

14. A method of driving an liquid crystal display (LCD) having a liquid crystal panel including gate lines and data lines arranged in a matrix, a gate driver generating a gate signal to activate the gate lines, a data driver for supplying image data to the data lines, and a power supply for generating and supplying a power supply voltage to the gate driver and the data driver, the method comprising:

displaying the image data on the liquid crystal panel in response to the gate signal when the power supply voltage is present at a high voltage; and

discharging a voltage of the liquid crystal panel by a discharge signal during a predetermined time interval after the power supply voltage is shut off,

wherein the power supply voltage is a high level when power is on and the power supply voltage is a low level when power is off,

wherein the gate signal includes a gate high voltage and a gate low voltage,

wherein the discharge signal is a voltage with a level equal to level of the gate high voltage, is generated when the power supply voltage is the low level and is supplied to the gate lines of the liquid crystal panel to discharge a residual voltage of the liquid crystal panel,

wherein the predetermined time interval is between the power supply voltage changing from a high level to a low level and the gate signal changing from the gate high voltage to the gate low voltage,

wherein the gate signal on a first gate line is sent back to the gate driver as a gate driver control signal for a second gate line.

15. The method according to claim 14 , wherein the discharge signal is supplied to the gate lines during at least a portion of the predetermined time interval.

16. The method according to claim 14 further comprising:

inputting the gate driver control signal into a logic controller;

outputting from the logic controller one of the high level state voltage and a low level state voltage according to the gate driver control signal when the power supply voltage is at a high voltage;

outputting from the shift register one of a gate high voltage and a gate low voltage according to the output from the logic controller when the power supply voltage is at the high voltage;

outputting a high level state voltage from the logic controller to substitute the gate driver control signal when the power supply voltage is at a low voltage;

outputting the gate high voltage from the shift register when the output from the logic controller is the high level state voltage.