Granted Patent B2

US 7,262,723 · App. 11/451,229 · Granted Aug 28, 2007

Abstract

Claims (27)

1. A compensation circuit for a digital/analogue converter, which is clocked by a clock signal comprising a jitter and converts a digital input data signal into an analogue output data signal comprising a jitter error due to said jitter; said compensation circuit comprising:

a measurement circuit for measuring said jitter; and

a modelling circuit for generating a digital modelled jitter error signal which simulates said jitter error dependent on said measured jitter and said digital input data signal;

wherein said digital modelled jitter error signal is subtracted from said digital input data signal.

2. The circuit of claim 1 , wherein a noise shaper for forming a quantization noise spectrum is connected upstream of said digital/analogue converter.

3. The circuit of claim 2 , wherein said noise shaper comprises a feedback loop and said digital modelled jitter error signal is fed into said feedback loop.

4. The circuit of claim 2 , wherein said noise shaper comprises:

an input for receiving a digital data signal comprising a word width of n data bits;

a separation circuit which separates said data signal into m most significant data bits and into k least significant data bits; and

an output for outputting said m most significant data bits as said digital input data signal to said digital/analogue converter.

5. The circuit of claim 4 , wherein said k least significant data bits are fed back to said input of said noise shaper via a digital feedback filter.

6. The circuit of claim 5 , wherein a first subtractor is connected upstream of said digital feedback filter; said first subtractor subtracting said digital modelled jitter error signal from said least significant data bits.

7. The circuit of claim 4 , wherein an amplitude limiter is connected upstream of said separation circuit of said noise shaper.

8. The circuit of claim 1 , wherein an analogue/digital converter is provided between said measurement circuit and said modelling circuit; said analogue/digital converter converting said measured jitter into a digital jitter value.

9. The circuit of claim 8 , wherein an averaging circuit for forming an average of said measured jitter can be connected upstream of said analogue/digital converter by means of a switch.

10. The circuit of claim 1 , wherein said modelling circuit comprises:

a delay element for generating a delayed digital input item by delaying an input data item of said digital input signal by one clock pulse period;

a second subtractor which subtracts said delayed digital input data item from said digital input data item to generate a differential value;

a mixer which multiplies said jitter value output by said analogue/digital converter by said differential value in order to generate a product value; and

a weighting circuit which applies a weighting to said generated product value in order to generate a jitter error value of said modelled jitter error signal.

11. The circuit of claim 1 , wherein said clock signal is generated by a PLL circuit.

12. The circuit of claim 11 , wherein said PLL circuit is a ring oscillator PLL circuit.

13. The circuit of claim 10 , wherein said weighting circuit comprises:

a first multiplier for weighting said product value with the inverse clock pulse period of said clock signal and

a second multiplier for weighting with a selectable scaling factor connected in series with said first multiplier.

14. The circuit of claim 13 , wherein an amplitude limiter is connected downstream of said weighting circuit provided within said modelling circuit.

15. The circuit of claim 1 , wherein said measurement circuit is formed by an analogue switched capacitor measurement circuit.

Assignments (8)