Integrated circuit and method for manufacturing an integrated circuit
An integrated circuit is disclosed that includes a component region with at least one NDMOS transistor and at least one PDMOS transistor and a substrate, which is isolated from the component region by a dielectric, whereby the component region, dielectric, and substrate form a first substrate capacitance standardized to a unit area in a first region of the PDMOS transistor and a second substrate capacitance standardized to said unit area in a second region of the NDMOS transistor, and whereby the first substrate capacitance standardized to said unit area is reduced in comparison to the second substrate capacitance standardized to said unit area.
1 . An integrated circuit comprising:
a component region having at least one NDMOS transistor and at least one PDMOS transistor; and
a substrate that is isolated from the component region by a dielectric, the component region, dielectric, and substrate forming a first substrate capacitance standardized to a unit area in a first region of the PDMOS transistor and a second substrate capacitance standardized to the unit area in a second region of the NDMOS transistor,
wherein the first substrate capacitance standardized to the unit area is reduced in comparison with the second substrate capacitance standardized to the unit area.
2 . The integrated circuit according to claim 1 , wherein the first substrate capacitance standardized to the unit area is reduced in comparison with the second substrate capacitance standardized to the unit area by a greater first thickness of the dielectric in the first region of the PDMOS transistor in comparison with a second thickness of the dielectric in the second region of the NDMOS transistor.
3 . The integrated circuit according to claim 2 , wherein a width of the first region is greater than the first thickness of the dielectric in the first region.
4 . The integrated circuit according to claim 1 , wherein the first substrate capacitance standardized to the unit area is reduced in comparison with the second capacitance standardized to the unit area by removing the substrate in the first region of the PDMOS transistor.
5 . The integrated circuit according to claim 1 , wherein the first region is a transition region of an N-well and a P-well of the PDMOS transistor.
6 . The integrated circuit according to claim 1 , wherein a plurality of PDMOS transistors are formed in the first region and/or a plurality of NDMOS transistors are formed in the second region.
7 . The integrated circuit according to claim 1 , wherein the first region is spatially distanced from each NDMOS transistor.
8 . A method for manufacturing an integrated circuit, the method comprising the steps of:
providing a substrate, a dielectric that is adjacent to the substrate, and a semiconductor region that is adjacent to the dielectric;
forming in the semiconductor region at least one NDMOS transistor;
forming in the semiconductor region at least one PDMOS transistor; and
forming the dielectric thicker in a first region of the PDMOS transistor than in a second region of the NDMOS transistor to produce the dielectric.
9 . A method for manufacturing an integrated circuit, the method comprising the steps of:
providing a dielectric adjacent to a substrate and a semiconductor region, which is isolated from the substrate by the dielectric;
forming at least one NDMOS transistor in the semiconductor region;
forming at least one PDMOS transistor in the semiconductor region; and
removing the substrate in a first region that is below the PDMOS transistor.
10 . The method according to claim 9 , wherein the-substrate is removed by etching.