III-nitride semiconductor device fabrication
View Patent ↗A method of fabricating a III-nitride power semiconductor device which includes selective prevention of the growth of III-nitride semiconductor bodies to selected areas on a substrate in order to reduce stresses and prevent cracking.
1. A method of fabricating a III-nitride semiconductor device, comprising:
forming a III-nitride growth inhibitor body over a surface of a substrate;
selectively removing portions of said III-nitride growth inhibitor body to expose portions of said substrate to serve as a III-nitride growth surface;
forming a trench around at least one of said exposed portions, said trench extending below said III-nitride growth surface;
filling said trench, a top surface of said filled trench generally coplanar with and laterally extending said III-nitride growth surface; and
growing a III-nitride semiconductor body over at least one of said exposed portions, said III-nitride semiconductor body being surrounded by said III-nitride growth inhibitor body;
wherein said III-nitride growth inhibitor body defines the outer boundary of said III-nitride semiconductor device.
2. The method of claim 1 , wherein said III-nitride semiconductor body includes a buffer layer on said at least one of said exposed portions and a III-nitride semiconductor power device formed over said buffer layer.
3. The method of claim 2 , wherein said buffer layer is comprised of AlN.
4. The method of claim 2 , wherein said buffer layer is graded.
5. The method of claim 2 , wherein said buffer layer is comprised of graded AlN.
6. The method of claim 2 , wherein said III-nitride power semiconductor device includes a GaN body and an AlGaN body over said GaN body.
7. The method of claim 1 , wherein said III-nitride growth inhibitor body is comprised of silicon dioxide.
8. The method of claim 1 , wherein said III-nitride growth inhibitor body is comprised of silicon nitride.
9. The method of claim 1 , wherein said III-nitride growth inhibitor body is waffled.
10. The method of claim 1 , wherein said trench extends into the body of said substrate.
11. The method of claim 1 , further comprising filling said trench with a III-nitride growth inhibitor body.
12. The method of claim 1 , further comprising damaging the crystal structure of a region below at least one of said exposed portions to form an amorphous region.
13. The method of claim 1 , wherein said substrate is comprised of silicon.
14. The method of claim 1 , wherein said substrate is comprised of silicon carbide.
15. The method of claim 1 , wherein said substrate is comprised of sapphire.
16. The method of claim 1 , wherein a III-nitride semiconductor body includes a first III-nitride semiconductor body comprised of one alloy from the InAlGaN system, and another alloy from the InAlGaN system.
17. The method of claim 1 , wherein said III-nitride growth inhibitor body is selectively removed to form a grid pattern on said substrate.
18. The method of claim 1 , wherein said growth surface is at least one millimeter square.
19. The method of claim 1 , wherein said III-nitride growth inhibitor body defines the height of said III-nitride device.
20. The method of claim 19 , wherein said height is at least one micron.
21. A method of fabricating a III-nitride based semiconductor device, comprising:
forming III-nitride growth barriers over a surface of a substrate, each of said III-nitride growth barriers surrounding a corresponding III-nitride semiconductor growth surface;
forming a trench around at least one of said III-nitride semiconductor growth surfaces, said trench extending below said III-nitride growth surface;
filling said trench, a top surface of said filled trench generally coplanar with and laterally extending said III-nitride semiconductor growth surface; and
growing a III-nitride semiconductor body over at least one of said defined III-nitride semiconductor growth surfaces;
wherein each of said III-nitride growth barriers defines the outer boundary of a respective semiconductor device.
22. A method according to claim 21 , wherein said barriers are comprised of silicon dioxide.
23. A method according to claim 21 , wherein said barriers are comprised of silicon nitride.
24. A method according to claim 21 , wherein said substrate is comprised of silicon.
25. A method according to claim 21 , wherein said substrate is comprised of silicon carbide.
26. A method according to claim 21 , wherein said substrate is comprised of sapphire.
27. A method according to claim 21 , further comprising growing an interlayer on at least one of said growth surfaces and then growing a III-nitride semiconductor body over said interlayer.
28. A method according to claim 27 , wherein said interlayer is comprised of AlN.
29. A method according to claim 27 , wherein said interlayer is comprised of graded AlN.
30. A method according to claim 21 , wherein said III-nitride semiconductor body is a heterojunction that includes one III-nitride semiconductor body comprised of one semiconductor alloy from the InAlGaN system and another III-nitride semiconductor body comprised of another semiconductor alloy from the InAlGaN system.
31. A method according to claim 21 , wherein at least one of said growth surfaces is at least one millimeter square.
32. A method according to claim 21 , wherein said growth barriers define the height of said III-nitride based semiconductor devices.
33. A method according to claim 32 , wherein the height is at least one micron.
34. A method according to claim 2 , wherein said buffer layer is a graded III-nitride material from the InAlGaN system.
35. A method according to claim 27 , wherein said interlayer is a graded III-nitride material from the InAlGaN system.
36. A method according to claim 2 , wherein said buffer layer is comprised of multiple layers of III-nitride semiconductor from the InAlGaN system, each layer being of a different composition.
37. A method according to claim 27 , wherein said interlayer is comprised of multiple layers of III-nitride semiconductor from the InAlGaN system each layer being of a different composition.