Granted Patent B2

US 7,944,945 · App. 11/453,795 · Granted May 17, 2011

Abstract

Claims (37)

1. An apparatus for use in a communications network for processing at least one of an STM-n (Synchronous Transport Module-n) and STS-m (Synchronous Transport Signal-m) type data frames, wherein the apparatus comprises at least one of an STM-n and STS-m line interface unit operable to receive STM-n and STS-m type data frames from a communications network and processor means operable to receive data from at least one of an STM-n and STS-m frame coming from said line Interface unit to:

i) segment the whole of said received frame into m groups of p successive bytes, wherein each group comprises payload data and overhead of the received frame;

ii) generate for each group an associated control header containing data that represents a position of each group within the at least one of an STM-n and STS-m frame; and

iii) encapsulate each group and the associated control header in a payload data field of an Ethernet frame wherein timing information is transported with the payload data field.

2. The apparatus according to claim 1 , wherein said processor means are operable to:

i) perform said segmentation when the at least one of an STM-n and STS-m frame data is received;

ii) associate a control header with a group as soon as the group has been formed by said segmentation;

iii) encapsulate the group and the associated control header in the Ethernet frame as soon as said control header has been associated with the group; and

iv) atoll continue to segment and associate a control header with an Ethernet frame until m Ethernet frames are created; and to transmit the resulting m Ethernet frames successively at a given period.

3. The apparatus according to claim 1 , wherein m is equal to 9 and p is equal to 270.

4. The apparatus according to claim 1 , wherein said Ethernet frame contains data that represents negative justification, no justification, or positive justification information.

5. The apparatus according to claim 4 , wherein said control header comprises one or more stuffing bits that represents negative justification information.

6. The apparatus according to claim 4 , wherein each group of p bytes comprises one or more stuffing bits that represent positive justification information.

7. The apparatus according to claim 5 , wherein each group of p bytes comprises one or more stuffing bits that represent positive justification information, and wherein said control header contains control data that represents said stuffing bits.

8. The apparatus according to claim 1 , wherein said processor means are operable to place in an information field of said Ethernet frame data that indicates that their payload data field contains a portion of an encapsulated the at least one of an STM-n and STS-m frame.

9. The apparatus according to claim 8 , wherein said information field is the “Type” field.

10. Frame switching equipment for use in an asynchronous communications network, wherein said frame switching equipment comprises:

at least one Ethernet frame switch that has at least one input operable to receive Ethernet frames in which m groups of p successive bytes and their generated corresponding control headers that represent positions of the m groups of at least one of an STM-n (Synchronous Transport Module-n) and STS-m (Synchronous Transport Signal-m) frame has been encapsulated in payload field of the Ethernet frames, wherein each of the m groups of the p successive bytes of the at least one of an STM-n and STS-m frame comprises payload data and overhead data, and wherein timing information is transported with the payload data, and wherein said frame switching equipment is operable to switch each received Ethernet frame to an output selected from at least two outputs; and

wherein the frame switching equipment is configured to switch each received Ethernet frame as a function of a destination port address designated in the control header of the Ethernet frame.

11. The apparatus of claim 10 , wherein the frame switching equipment further comprises at least one STM-n and STS-m logical line termination board where each of the at least one STM-n and STS-m logical line termination board comprises:

a unique destination port address; and

is configured to the extract from the received Ethernet frames the groups of p bytes comprising the received Ethernet frames to reconstitute at least one of an STM-n and STS-m frame.

12. The apparatus of claim 11 , wherein the at least one STM-n and STS-m logical line termination board comprises at least one of a line termination board dedicated to channelized data.

13. The apparatus of claim 12 , wherein the at least one line termination board receives Ethernet frames in parallel from the at least one frame switching equipment.

14. A telecommunications equipment apparatus configured to:

segment at least one of an STM-n (Synchronous Transport Module-n) and STS-m (Synchronous Transport Signal-m) frame into m groups of p successive bytes where each group comprises payload data and overhead of the at least one of an STM-n and STS-m frame;

generate for each group an associated control header containing data that represents a position of a group within the at least one of an STM-n and STS-m frame; and

encapsulate each group and the associated control header in a payload field of an Ethernet frame wherein timing information is transported with the payload field.

15. The apparatus of claim 14 , wherein the telecommunications equipment further comprises at least one communications network processor operable to receive the at least one of an STM-n and STS-m frame and communicate the Ethernet frame to at least one Ethernet frame switch, the at least one Ethernet frame switch being operable to receive the Ethernet frame and communicate the Ethernet frame to at least one of an STM-n and STS-m logical line termination board, and the at least one of an STM-n and STS-m logical line termination board configured to receive the Ethernet frame; and

wherein the at least one communications network processor is communicatively coupled with the at least one Ethernet frame switch, and wherein the at least one Ethernet frame switch is communicatively coupled with the at least one of an STM-n and STS-m logical line termination board; and

wherein the at least one communications network processor is configured to communicate the Ethernet frame to the at least one Ethernet frame switch; and

wherein the at least one Ethernet frame switch switches the Ethernet frame to the at least one of an STM-n and STS-m logical line termination board as a function of a destination port address designated in a header of the Ethernet frame.

16. The apparatus of claim 15 , wherein the at least one communications network processor communicates the at least one of an STM-n and STS-m frame in an approximately 125 micro second time frame.

17. The apparatus of claim 15 , wherein the at least one Ethernet frame switch is configured to communicate in parallel at least one Ethernet frame to the at least one STM-n and STS-m logical line termination board.

18. The apparatus of claim 15 , wherein the at least one Ethernet frame switch and the at least one STM-n and STS-m logical line termination board reside in an aTCA rack.

19. The apparatus of claim 15 , wherein the control header comprises a plurality of stuffing bits that represents justification information where the justification information is at least one of negative justification, positive justification and no justification.

20. The apparatus of claim 1 , wherein the control header and the overhead are different.

Assignments (10)