Array substrate for liquid crystal display device having defect repair structure
View Patent ↗An array substrate for a liquid crystal display device includes a gate line and a first storage electrode on a substrate, a data line crossing the gate line to define a first pixel region, a thin film transistor connected to the gate line and the data line, a second storage electrode over the first storage electrode, a first pixel electrode in the first pixel region, the first pixel electrode connected to the thin film transistor and the second storage electrode, the second storage electrode including a first portion over the first storage electrode and a second portion in a second pixel region adjacent to the first pixel region, and a repair pattern for the first pixel region between the second storage electrode and a second pixel electrode in the second pixel region.
1. An array substrate for a liquid crystal display device, comprising:
a gate line and a first storage electrode on a substrate;
a data line crossing the gate line to define a first pixel region;
a thin film transistor connected to the gate line and the data line;
a second storage electrode over the first storage electrode and disposed on the same layer as the data line, the second storage electrode including a first portion over the first storage electrode and a second portion in a second pixel region adjacent to the first pixel region;
a first pixel electrode in the first pixel region, the first pixel electrode connected to the thin film transistor and the second storage electrode, the first pixel electrode overlapping the first portion of the second storage electrode; and
a repair pattern for the first pixel region between the second storage electrode and a second pixel electrode in the second pixel region, the repair pattern partially overlapping the second portion of the second storage electrode and the second pixel electrode.
2. The array substrate according to claim 1 , further comprising a gate insulating layer between the gate line and the data line and between the first storage electrode and the second storage electrode.
3. The array substrate according to claim 1 , wherein the thin film transistor includes a gate electrode connected to the gate line, a semiconductor layer over the gate electrode, a source electrode connected to the data line and a drain electrode spaced apart from the source electrode.
4. The array substrate according to claim 3 , further comprising a passivation layer between the thin film transistor and the first pixel electrode and between the second storage electrode and the first pixel electrode.
5. The array substrate according to claim 4 , wherein the passivation layer includes a drain contact hole that exposes a portion of the drain electrode.
6. The array substrate according to claim 5 , wherein the first pixel electrode is connected to the drain electrode via the drain contact hole.
7. The array substrate according to claim 4 , wherein the passivation layer includes a storage contact hole over a portion of the second storage electrode.
8. The array substrate according to claim 7 , wherein the first pixel electrode is connected to the second storage electrode via the storage contact hole.
9. The array substrate according to claim 1 , wherein the repair pattern is disposed at the same layer as the gate line.
10. The array substrate according to claim 1 , wherein the repair pattern includes the same material as the gate line.
11. The array substrate according to claim 1 , wherein the second storage electrode includes the same material as the data line.
12. The array substrate according to claim 1 , wherein the first storage electrode occupies a portion of the gate line for the second pixel region.
13. The array substrate according to claim 1 , wherein the second storage electrode has a “T” shape.
14. An array substrate for a liquid crystal display device, comprising:
a gate line and a first storage electrode on a substrate;
a data line crossing the gate line to define a first pixel region;
a first thin film transistor connected to the gate line and the data line;
a second storage electrode over the first storage electrode and disposed on the same layer as the data line, the second storage electrode including a first portion over the first storage electrode and a second portion in a second pixel region adjacent to the first pixel region;
a first pixel electrode in the first pixel region, the first pixel electrode connected to the second storage electrode, the first pixel electrode overlapping the first portion of the second storage electrode; and
a repair pattern for the first pixel region between the second storage electrode and a second pixel electrode in the second pixel region, the repair pattern partially overlapping the second portion of the second storage electrode and the second pixel electrode, wherein the first pixel electrode is connected to the second pixel electrode through the repair pattern.