Memory controller and data processing system
View Patent ↗A memory controller and data processor have their operation mode switched from the page-on mode for high-speed access to a same page to the page-off mode in response to consecutive events of access to different pages, so that the memory access is performed at a high speed and low power consumption.
1. A semiconductor device comprising:
a volatile memory which has a plurality of word lines, bit lines, and memory cells; and a memory controller controlling said volatile memory to operate in a first mode or a second mode, and including a counter counting a number of successive accesses to different word lines,
wherein during the first mode, the memory controller controls the volatile memory to pre-charge the plurality of bit lines after a read access,
wherein during the second mode, the memory controller outputs signals for next read access without pre-charging the plurality of bit lines after a read access, and
wherein the memory controller changes from the second mode to the first mode after different word lines are accessed a predetermined number of times successively, a number of the predetermined times being set in the counter, wherein the first mode is a page off mode, and wherein the second mode is a page on mode.
2. A semiconductor device according to claim 1 , wherein the volatile memory is an SDRAM.
3. A semiconductor device according to claim 1 ,
wherein the memory controller and the memory are molded in a same package.
4. A semiconductor device according to claim 1 ,
wherein the word lines are selected by row address, and
wherein during the second mode, if an access to a same word line continues, the memory controller does not output a row address to the memory.
5. A semiconductor device according to claim 1 ,
wherein the number of predetermined times is set into the counter by a CPU.
6. A semiconductor device according to claim 1 , wherein the memory controller changes from the first mode to the second mode when a same word line is accessed.
7. A semiconductor device comprising:
a memory controller controlling a memory which has a plurality of word lines, bit lines, and memory cells, operating in a first mode or a second mode, and including a counter counting a number of successive accesses to different word lines,
wherein during the first mode, the memory controller controls the memory to pre-charge the plurality of bit lines after a read access,
wherein during the second mode, the memory controller outputs signals for next read access without pre-charging the plurality of bit lines after a read access, and
wherein the memory controller changes from the second mode to the first mode after different word lines are accessed a predetermined number of times successively, a number of the predetermined times being able to be set in the counter,
wherein the memory controller further comprises, a page access decision circuit, a mode changing circuit, and an address generating circuit,
wherein the word lines are selected by row address, and
wherein the page decision circuit compares a row address inputted to the memory controller and the previous row address,
wherein the mode changing circuit receives signals from the page decision circuit and counts the number of successive accesses to different word lines by the counter, and
wherein the address generating circuit receives signals from, the page decision circuit and from the mode changing circuit and outputs a command and an address to the memory.