IP Library Granted Patent US 7,417,492
Granted Patent B2
US 7,417,492 · App. 11/453,982 · Granted Aug 26, 2008

Regulator

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Quick Facts
Patent No.
US 7,417,492
App. No.
11/453,982
Granted
Aug 26, 2008
Kind
B2
Abstract

A regulator includes a digital voltage detection unit for generating a digital voltage detection signal by detecting a digital value of a voltage level of an input voltage; a variable gain amplifying unit for amplifying the input voltage in an amplifying ratio according to a gain control signal; and a gain control unit for receiving the digital voltage detection signal to thereby generate the gain control signal.

Claims (22)

1. A regulator, comprising:

a digital voltage detection unit for generating a digital voltage detection signal by detecting a digital value of a voltage level of an input voltage;

a variable gain amplifying unit for amplifying the input voltage in an amplifying ratio according to a gain control signal; and

a gain control unit for receiving the digital voltage detection signal to thereby generate the gain control signal, wherein

the gain control unit is a digital operational unit for comparing the digital voltage detection signal with a target value to thereby adjust a gain value of the variable gain amplifying unit so that the target value can be obtained by applying the gain value to the digital voltage detection signal.

2. The regulator as recited in claim 1 , wherein the variable gain amplifying unit includes:

an operational amplifier for receiving the input voltage through an inversion input terminal;

a first variable resistor whose one terminal and the other terminal are coupled to a non-inversion input terminal of the operational amplifier and a ground voltage respectively; and

a second variable resistor whose one terminal and the other terminal are coupled to the non-inversion input terminal of the operational amplifier and an output terminal of the operational amplifier.

3. The regulator as recited in claim 2 , wherein the variable gain amplifying unit further includes a unit gain operational amplifier for buffering an output of the operational amplifier.

4. The regulator as recited in claim 1 , wherein the variable gain amplifying unit includes:

an operational amplifier for receiving the input voltage through an inversion input terminal;

a variable resistor whose one terminal and the other terminal are coupled to a non-inversion input terminal of the operational amplifier and a ground voltage respectively; and

a fixed resistor whose one terminal and the other terminal are coupled to the non-inversion input terminal of the operational amplifier and an output terminal of the operational amplifier.

5. The regulator as recited in claim 1 , wherein the variable gain amplifying unit includes:

an operational amplifier for receiving the input voltage through an inversion input terminal;

a fixed resistor whose one terminal and the other terminal are coupled to a non-inversion input terminal of the operational amplifier and a ground voltage respectively; and

a variable resistor whose one terminal and the other terminal are coupled to the non-inversion input terminal of the operational amplifier and an output terminal of the operational amplifier.

6. The regulator as recited in claim 1 , wherein the digital voltage detection unit includes:

a counter for counting a predetermined operational clock;

a voltage detector for comparing the input voltage with a comparison voltage which increases in proportion to a counted number of the counter to thereby output a comparison result as a logic value; and

a serial input parallel output (SIPO) block for receiving an output logic value stream which is a serial digital data outputted as the comparison result from the voltage detector to thereby generate the digital voltage detection signal which is a parallel digital data.

Assignments (6)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 7, 2025
From: MAGNACHIP MIXED-SIGNAL, LTD.
To: MAGNACHIP SEMICONDUCTOR, LTD.
Reel/Frame 071813/0800 →
NUNC PRO TUNC ASSIGNMENT Recorded Mar 14, 2024
From: MAGNACHIP SEMICONDUCTOR, LTD.
To: MAGNACHIP MIXED-SIGNAL, LTD.
Reel/Frame 066878/0875 →
CORRECTIVE ASSIGNMENT TO CORRECT THE RECEIVING PARTY ADDRESS PREVIOUSLY RECORDED AT REEL: 024563 FRAME: 0807. ASSIGNOR(S) HEREBY CONFIRMS THE RELEASE BY SECURED PARTY. Recorded Nov 25, 2014
From: US BANK NATIONAL ASSOCIATION
To: MAGNACHIP SEMICONDUCTOR LTD.
Reel/Frame 034469/0001 →
RELEASE OF SECURITY INTEREST Recorded Jun 22, 2010
From: U.S. BANK NATIONAL ASSOCIATION
To: MAGNACHIP SEMICONDUCTOR LTD.
Reel/Frame 024563/0807 →
AFTER-ACQUIRED INTELLECTUAL PROPERTY KUN-PLEDGE AGREEMENT Recorded Feb 18, 2009
From: MAGNACHIP SEMICONDUCTOR, LTD.
To: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL TRUSTEE
Reel/Frame 022277/0133 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 16, 2006
From: HONG, BYUNG-IL
To: MAGNACHIP SEMICONDUCTOR, LTD.
Reel/Frame 018004/0331 →