Facilitating fast scanning for control transfer instructions in an instruction fetch unit

1. A method for performing a fast-scanning operation to generate fetch bundles in an instruction fetch unit (IFU) of a processor, comprising:

obtaining a cache line containing instructions at the IFU;

performing a complete-scanning operation on the cache line in a complete-scanning circuit to identify control transfer instructions (CTIs) by scanning a first set of instructions in the cache line;

at the same time that the complete-scanning operation is performed, separately performing the fast-scanning operation in a fast-scanning circuit to identify CTIs in a group of initial instructions in the cache line by scanning a second set of instructions in the cache line, wherein the second set of instructions is a subset of the first set of instructions that consists of a smaller number of instructions than the first set of instructions;

obtaining results from the fast-scanning operation before results of the complete-scanning operation are available;

using the results from the fast-scanning operation to form an initial fetch bundle containing initial instructions; and

sending the initial fetch bundle to an instruction-issue unit.

2. The method of claim 1 , wherein when results from the complete-scanning operation become available, the method further involves:

using the results from the complete-scanning operation to form other fetch bundles containing other instructions from the cache line; and

sending the other fetch bundles to the instruction-issue unit.

3. The method of claim 1 , wherein performing the fast-scanning operation involves:

using a program counter to identify the group of initial instructions;

determining locations of CTIs in the group of initial instructions;

determining which initial instructions are valid based on the locations of the CTIs in the group of initial instructions; and

generating corresponding valid signals for the group of initial instructions.

4. The method of claim 3 , wherein while performing the fast-scanning operation, if the program counter indicates that the group of initial instructions is located at the end of the cache line, the method further comprises generating a fast end-of-line (EOL) signal, which allows another cache line fetch to be launched.

5. The method of claim 3 , wherein while determining which initial instructions in the group of initial instructions are valid, conditional-branch instructions are predicted to be taken.

6. The method of claim 5 , wherein while determining which initial instructions are valid, a small-forward branch instruction is determined to be valid, but a following delay slot is determined to be not valid, which causes the following delay slot to be included in a following fetch bundle, thereby allowing additional time for a branch target to be computed.

7. The method of claim 1 , wherein using the results from the fast-scanning operation to form the initial fetch bundle involves:

determining which initial instructions in the group of initial instructions are valid by examining one or more valid signals produced by the fast-scanning operation; and

forming the initial fetch bundle from the valid initial instructions.

8. An apparatus that performs a fast-scanning operation to generate fetch bundles in an instruction fetch unit (IFU) of a processor, comprising:

a receiving mechanism configured to receive a cache line containing instructions;

a complete-scanning circuit configured to perform a complete-scanning operation on the cache line to identify control transfer instructions (CTIs) by scanning a first set of instructions in the cache line;

a fast-scanning circuit that operates in parallel with and separately from the complete-scanning circuit, wherein the fast-scanning circuit is configured to perform the fast-scanning operation to identify CTIs in a group of initial instructions in the cache line by scanning a second set of instructions in the cache line, wherein the second set of instructions is a subset of the first set of instructions that consists of a smaller number of instructions than the first set of instructions;

a bundle-forming mechanism, which is configured to,

obtain results from the fast-scanning operation before results of the complete-scanning operation are available,

use the results from the fast-scanning operation to form an initial fetch bundle containing initial instructions, and to

send the initial fetch bundle to an instruction-issue unit.

9. The apparatus of claim 8 , wherein when results from the complete-scanning circuit become available, the bundle-forming mechanism is configured to:

use the results from the complete-scanning circuit to form other fetch bundles containing other instructions from the cache line; and to

send the other fetch bundles to the instruction-issue unit.

10. The apparatus of claim 8 , wherein the fast-scanning circuit is configured to:

use the program counter to identify the group of initial instructions;

locate CTIs in the group of initial instructions;

determine which initial instructions are valid based on locations of the CTIs in the group of initial instructions; and to

generate corresponding valid signals for the group of initial instructions.

11. The apparatus of claim 10 , wherein while performing the fast-scanning operation, if the program counter indicates that the group of initial instructions is located at the end of the cache line, the fast-scanning circuit is configured to generate a fast end-of-line (EOL) signal, which allows another cache line fetch to be launched.

12. The apparatus of claim 10 , wherein while determining which initial instructions in the group of initial instructions are valid, the fast-scanning circuit predicts conditional-branch instructions to be taken.

13. The apparatus of claim 12 , wherein while determining which initial instructions are valid, a small-forward branch instruction is determined to be valid, but the following delay slot is determined to be not valid, which causes the following delay slot to be included in a following fetch bundle, thereby allowing additional time for a branch target to be computed.

14. The apparatus of claim 8 , wherein while using the results from the fast-scanning operation to form the initial fetch bundle, the bundle-forming mechanism is configured to:

determine which initial instructions in the group of initial instructions are valid by examining one or more valid signals produced by the fast-scanning circuit; and to

form the initial fetch bundle from the valid initial instructions.

15. A computer system performs a fast-scanning operation to generate fetch bundles in an instruction fetch unit (IFU) of a processor, comprising:

a processor;

a memory;

an IFU within the processor;

a receiving mechanism within the IFU, which is configured to receive a cache line containing instructions;

a complete-scanning circuit within the IFU, which is configured to perform a complete-scanning operation on the cache line to identify control transfer instructions (CTIs) by scanning a first set of instructions in the cache line;

a fast-scanning circuit within the IFU that operates in parallel with and separately from the complete-scanning circuit, wherein the fast-scanning circuit is configured to perform the fast-scanning operation to identify CTIs in a group of initial instructions in the cache line by scanning a second set of instructions in the cache line, wherein the second set of instructions is a subset of the first set of instructions that consists of a smaller number of instructions than the first set of instructions;

a bundle-forming mechanism within the IFU, which is configured to,

obtain results from the fast-scanning operation before results of the complete-scanning operation are available,

use the results from the fast-scanning operation to form an initial fetch bundle containing initial instructions, and to

send the initial fetch bundle to an instruction-issue unit.

16. The computer system of claim 15 , wherein when results from the complete-scanning circuit become available, the bundle-forming mechanism is configured to:

use the results from the complete-scanning circuit to form other fetch bundles containing other instructions from the cache line; and to

send the other fetch bundles to the instruction-issue unit.

17. The computer system of claim 15 , wherein the fast-scanning circuit is configured to:

use the program counter to identify the group of initial instructions;

locate CTIs in the group of initial instructions;

determine which initial instructions are valid based on locations of the CTIs in the group of initial instructions; and to

generate corresponding valid signals for the group of initial instructions.

18. The computer system of claim 17 , wherein while performing the fast-scanning operation, if the program counter indicates that the group of initial instructions is located at the end of the cache line, the fast-scanning circuit is configured to generate a fast end-of-line (EOL) signal, which allows another cache line fetch to be launched.

19. The computer system of claim 17 , wherein while determining which initial instructions in the group of initial instructions are valid, the fast-scanning circuit predicts conditional-branch instructions to be taken.

20. The computer system of claim 19 , wherein while determining which initial instructions are valid, a small-forward branch instruction is determined to be valid, but the following delay slot is determined to be not valid, which causes the following delay slot to be included in a following fetch bundle, thereby allowing additional time for a branch target to be computed.

21. The computer system of claim 15 , wherein while using the results from the fast-scanning operation to form the initial fetch bundle, the bundle-forming mechanism is configured to:

determine which initial instructions in the group of initial instructions are valid by examining one or more valid signals produced by the fast-scanning circuit; and to

form the initial fetch bundle from the valid initial instructions.