Shift register
A shift register includes a signal generating circuit for generating an output signal at an output end of the shift register in response to a clock signal while the signal generating circuit is turned on, a driving circuit electrically coupled to the signal generating circuit for controlling the signal generating circuit in response to an input signal received from an input end of the shift register, a primary reset circuit electrically coupled to the signal generating circuit for turning off the signal generating circuit and resetting the output signal from the output end, and a feedback circuit electrically coupled to the output end and the major reset circuit for controlling the primary reset circuit in response to the output signal and the clock signal.
1. A shift register, comprising:
an output end;
an input end;
a signal generating circuit for generating an output signal at the output end in response to a clock signal while the signal generating circuit is turned on;
a driving circuit, electrically coupled to the signal generating circuit, for controlling the signal generating circuit in response to an input signal from the input end;
a primary reset circuit, electrically coupled to the signal generating circuit, for turning off the signal generating circuit and resetting an output signal from the output end; and
a feedback circuit, electrically coupled to the output end and the primary reset circuit, for controlling the primary reset circuit in response to the output signal and the clock signal, wherein the feedback circuit comprises:
a first thin film transistor (TFT) for outputting a feedback signal in response to the clock signal while the first TFT is turned on;
a second TFT for controlling the first TFT in response to the output signal from the output end;
a third TFT for resetting the feedback signal from the first TFT in response to the clock signal;
a fourth TFT for resetting the feedback signal from the first TFT in response to the output signal from the output end; and
a fifth TFT for resetting the signal from the second TFT while the fifth TFT is turned on.
2. The shift register of claim 1 , further comprising a secondary reset circuit, electrically coupled to the output end and the signal generating circuit, for turning off the signal generating circuit and resetting the output signal from the output end in response to the clock signal.
3. The shift register of claim 1 , wherein the input end is electrically coupled to an output end of a previous stage shift register.
4. The shift register of claim 1 , wherein the primary reset circuit comprises:
a sixth TFT for turning off the signal generating circuit while the sixth TFT is turned on by the feedback signal from the first TFT; and
a seventh TFT for resetting the output signal from the output end while the seventh TFT is turned on by the feedback signal from the first TFT.
5. A thin film transistor (TFT) liquid crystal display (LCD), comprising:
a display array; and
a gate driving circuit, having a plurality of stage shift registers coupled in a series, electrically connected to the display array, each stage shift register comprising:
an output end;
an input end;
a signal generating circuit for generating an output signal at the output end of the shift register while the signal generating circuit is turned on in response to a clock signal;
a driving circuit, electrically coupled to the signal generating circuit for controlling the signal generating circuit in response to an input signal from the input end;
a primary reset circuit, electrically coupled to the signal generating circuit for turning off the signal generating circuit and resetting an output signal from the output end; and
a feedback circuit, electrically coupled to the output end and the primary reset circuit for controlling the primary reset circuit in response to the output signal and the clock signal, wherein the feedback circuit comprises:
a first thin film transistor (TFT) for outputting a feedback signal while the first TFT is turned in response to the clock signal;
a second TFT for controlling the first TFT in response to the output signal from the output end of the shift register;
a third TFT for resetting the feedback signal from the first TFT in response to the clock signal;
a fourth TFT for resetting the feedback signal from the first TFT in response to the output signal from the output end; and
a fifth TFT for resetting the signal from the second TFT while the fifth TFT is turned on.
6. The LCD of claim 5 , wherein the shift register further comprises a secondary reset circuit, electrically coupled to the output end and the signal generating circuit for turning off the signal generating circuit and resetting the output signal from the output end in response to the clock signal.
7. The LCD of claim 5 , wherein the input end is, electrically coupled to an output end of a previous shift register.
8. The LCD of claim 5 , wherein the primary reset circuit comprises:
a sixth TFT for turning off the signal generating circuit while the sixth TFT is turned on by the feedback signal from the first TFT; and
a seventh TFT for resetting the output signal from the output end while the seventh TFT is turned on by the feedback signal from the first TFT.