Computer system having an apportionable data bus and daisy chained memory chips
View Patent ↗A memory system having a data bus coupling a memory controller and a memory. The data bus has a number of data bus bits. The data bus is programmably apportioned to a first portion dedicated to transmitting data from the memory controller to the memory and a second portion dedicated to transmitting data from the memory to the memory controller. The apportionment can be assigned by suitable connection of pins on a memory chip in the memory and the memory controller to logical values. Alternatively, the apportionment can be scanned into the memory controller and the memory at bring up time. In another alternative, the apportionment can be changed by suspending data transfer and dynamically changing the sizes of the first portion and the second portion.
1. A memory system comprising:
a memory controller;
a memory comprising a first memory chip and a second memory chip;
a first segmented unidirectional data bus for transmitting write data words, the first segmented data bus further comprising:
a first segment connected to the memory controller and to the first memory chip; and
a second segment connected to the first memory chip and to the second memory chip;
a second segmented unidirectional data bus for transmitting read data words, the second segmented unidirectional data bus further comprising:
a third segment connected to the memory controller and to the first memory chip;
a fourth segment connected to the first memory chip and to the second memory chip;
wherein a first read data word is received by the first memory chip from the fourth segment and stored on the first memory chip in a read data queue until the first memory chip has completed transmitting a second read data word on the third segment; the first read data word being transmitted from the read data queue onto the third segment when transmission of the second read data word on the third segment has been completed; and wherein the first read data word is associated with a third address/command word, and the second read data word is associated with a fourth address/command word;
wherein a first write data word is received by the first memory chip from the first segment and stored in a queue on the first memory chip until the first memory chip has completed transmitting a second write data word on the second segment, and wherein the first write data word is associated with a first address/command word and the second write data word is associated with a second address/command word; and wherein the first write data word is transmitted from the queue onto the second segment only if the first write data word is to be written to the second memory chip;
wherein the third address/command word was issued by the memory controller prior to the fourth address/command word; and
wherein each data word is identifiable with an ID (identifier) which is transmitted with the each data word, the ID usable by the memory controller to re-order the data words.