Thin film transistor and method of fabricating the same
View Patent ↗A thin film transistor and method of fabricating the same are provided. The thin film transistor includes: a metal catalyst layer formed on a substrate, and a first capping layer and a second capping layer pattern sequentially formed on the metal catalyst layer. The method includes: forming a first capping layer on a metal catalyst layer; forming and patterning a second capping layer on the first capping layer; forming an amorphous silicon layer on the patterned second capping layer; diffusing the metal catalyst; and crystallizing the amorphous silicon layer to form a polysilicon layer. The crystallization catalyst diffuses at a uniform low concentration to control a position of a seed formed of the catalyst such that a channel region in the polysilicon layer is close to a single crystal. Therefore, the characteristics of the thin film transistor device may be improved and uniformed.
1. A method of fabricating a thin film transistor comprising:
forming a metal catalyst layer on a substrate;
forming a first capping layer on the metal catalyst layer;
forming and patterning a second capping layer on the first capping layer;
forming an amorphous silicon layer on the patterned second capping layer;
diffusing the metal catalyst; and
crystallizing the amorphous silicon layer to form a polysilicon layer,
wherein the first capping layer and the patterned second capping layer are not removed after forming the polysilicon layer.
2. The method according to claim 1 , wherein the metal catalyst layer is formed by any one of a plasma chemical vapor deposition (CVD) method and a sputtering method.
3. The method according to claim 1 , wherein the first capping layer and the second capping layer are formed by a plasma enhanced chemical vapor deposition (PECVD) method.
4. The method according to claim 1 , wherein the metal catalyst diffuses through annealing.
5. The method according to claim 4 , wherein the annealing process is performed at a temperature of 200 to 700° C.
6. The method according to claim 1 , wherein the amorphous silicon layer is crystallized by an annealing process.
7. The method according to claim 6 , wherein the annealing process is performed at a temperature of 400 to 1000° C.
8. The method according to claim 1 , further comprising after forming the polysilicon layer, forming a channel layer.
9. The method according to claim 8 , wherein the channel layer is formed apart from an end of the patterned second capping layer by 1 to 5 μm.
10. A method of fabricating a thin film transistor, comprising:
forming a metal catalyst layer on a substrate;
forming and patterning a first capping layer on the metal catalyst layer;
forming a second capping layer on the patterned first capping layer;
forming an amorphous silicon layer on the second capping layer;
diffusing the metal catalyst; and
crystallizing the amorphous silicon layer to form a polysilicon layer,
wherein the patterned first capping layer and the second capping layer are not removed after forming the polysilicon layer.
11. The method according to claim 10 , wherein the metal catalyst layer is formed by any one of a plasma chemical vapor deposition (CVD) method and a sputtering method.
12. The method according to claim 10 , wherein the first capping layer and the second capping layer are formed by a plasma enhanced chemical vapor deposition (PECVD) method.
13. The method according to claim 10 , wherein the metal catalyst diffuses by an annealing process.
14. The method according to claim 13 , wherein the annealing process is performed at a temperature of 200 to 700° C.
15. The method according to claim 10 , wherein the amorphous silicon layer is crystallized by an annealing process.
16. The method according to claim 15 , wherein the annealing process is performed at a temperature of 400 to 1000° C.
17. The method according to claim 10 , further comprising after forming the polysilicon layer, forming a channel layer.
18. The method according to claim 17 , wherein the channel layer is formed apart from an end of the patterned first capping layer by 1 to 5 μm.