IP Library Granted Patent US 7,352,622
Granted Patent B2
US 7,352,622 · App. 11/461,256 · Granted Apr 1, 2008

Data arrangement and data arranging method in storage device

Assignee: Via Technologies, Inc.
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Quick Facts
Patent No.
US 7,352,622
App. No.
11/461,256
Granted
Apr 1, 2008
Kind
B2
Abstract

The disclosure relates to a data arranging method of a flash memory for improving access performance. The method includes steps of storing a first data sector to a page of the flash memory; storing a first data correction set corresponding to the first data sector in the page of the flash memory, wherein the first data correction set is next and contiguous to the first data sector; and repeating the two storing steps for storing a plurality of data sectors and a plurality of corresponding data correction sets until the page is formed.

Claims (36)

1. A data arrangement, comprising:

a plurality of data sectors stored in a page of a flash memory; and

a plurality of data correction sets stored in the page, wherein the data sectors and the data correction sets have a relation of one to one correspondence, each data correction set is generated by a data correction algorithm for detecting error in the corresponding data sector respectively, and each data correction set is next and contiguous to its corresponding data sector;

wherein one data correction set is divided into two data correction sub-sets, an error in one portion of the corresponding data sector is detected according to one data correction sub-set, and an error in the other portion of the corresponding data sector is detected according to the other data correction sub-set.

2. The data arrangement according to claim 1 , wherein a size of one data sector is 512 bytes and a size of one data correction set is 16 bytes.

3. The data arrangement according to claim 2 , wherein the page comprises 4 data sectors and 4 data correction sets.

4. The data arrangement according to claim 1 , wherein a size of one data sector is 128 bytes and a size of one data correction set is 4 bytes.

5. The data arrangement according to claim 1 , wherein the data correction algorithm is an ECC algorithm.

6. The data arrangement according to claim 1 further comprising a data access buffer having a size being equal to a total sizes of one data sector and one data correction set.

7. A data arranging method, comprising steps of:

storing a first data sector to a page of a flash memory;

storing a first data correction set corresponding to the first data sector in the page of the flash memory, wherein the first data correction set is next and contiguous to the first data sector;

repeating the two storing steps for storing a plurality of data sectors and a plurality of corresponding data correction sets until the page is formed;

providing a data access buffer having a size being equal to a total sizes of one data sector and one data correction set.

8. The data arranging method according to claim 1 , wherein a size of one data sector is 512 bytes and a size of one data correction set is 16 bytes.

9. The data arranging method according to claim 7 , wherein a size of one data sector is 128 bytes and a size of one data correction set is 4 bytes.

10. The data arranging method according to claim 7 , wherein each data correction set is generated by an ECC algorithm for detecting errors in its corresponding data sector.

11. The data arranging method according to claim 7 further dividing one data correction set into two data correction sub-sets for detecting at least one error in its corresponding data sector, wherein one error in a portion of its corresponding data sector can be detected by one data correction sub-set and one error in the other portion of the corresponding data sector can be detected by the other data correction sub-set.

12. A data arrangement for adjusting an error coverage rate, comprising:

a plurality of data sectors stored in a page of a flash memory; and

a plurality of data correction sets stored in the page, wherein the data sectors and the data correction sets have a relation of one to one correspondence, and one data correction set is divided into at least two data correction sub-sets for detecting at least one error in its corresponding data sector.

13. The data arrangement for adjusting an error coverage rate according to claim 12 , wherein a size of one data sector is 512 bytes and a size of one data correction set is 16 bytes.

14. The data arrangement for adjusting an error coverage rate according to claim 13 , wherein one data correction set is divided into two data correction sub-set and a size of each data correction sub-set is 8 bytes.

15. The data arrangement for adjusting an error coverage rate according to claim 12 , wherein the page comprises 4 data sectors and 4 data correction sets.

16. The data arrangement for adjusting an error coverage rate according to claim 12 , wherein each of the data correction sub-sets is generated by an ECC algorithm for detecting one error in a portion of the corresponding data sector.

17. The data arrangement for adjusting an error coverage rate according to claim 12 , wherein each data correction set is next and contiguous to its corresponding data sector.

18. The data arrangement for adjusting an error coverage rate according to claim 17 further comprising a data access buffer having a size being equal to a total sizes of one data sector and one data correction set.

19. A data arrangement, comprising:

a plurality of data sectors stored in a page of a flash memory;

a plurality of data correction sets stored in the page, wherein the data sectors and the data correction sets have a relation of one to one correspondence, each data correction set is generated by a data correction algorithm for detecting error in the corresponding data sector respectively, and each data correction set is next and contiguous to its corresponding data sector; and

a data access buffer having a size being equal to a total sizes of one data sector and one data correction set.

20. A data arranging method, comprising steps of:

storing a first data sector to a page of a flash memory;

storing a first data correction set corresponding to the first data sector in the page of the flash memory, wherein the first data correction set is next and contiguous to the first data sector;

repeating the two storing steps for storing a plurality of data sectors and a plurality of corresponding data correction sets until the page is formed; and

dividing one data correction set into two data correction sub-sets for detecting at least one error in its corresponding data sector, wherein an error in one portion of the corresponding data sector is detected according to one data correction sub-set and an error in the other portion of the corresponding data sector is detected according to the other data correction sub-set.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 31, 2006
From: CHIANG, CHIN-YI; KUO, TUNG-CHIH; TSENG, CHUN-HUA; CHANG, YU-WEI
To: VIA TECHNOLOGIES, INC.
Reel/Frame 018036/0711 →
Priority Claims (1)
TW 94128817 A · Aug 23, 2005 · national
Continuity (1)
Related Publication 20070061503A1 · Mar 15, 2007