Digital expander for generating multiple analog control signals particularly useful for controlling an oscillator
View Patent ↗An exemplary PLL circuit includes a VCO responsive to a plurality of sub-varactor control signals. A digital loop filter for the PLL digitally generates a varactor control word, which is digitally expanded into a plurality of digital values, each of which is conveyed to a corresponding one of a plurality of DACs. A multiplexer is configured to respectively convey the DAC output signals to a group of sub-varactor control signals according to the varactor control word, and to drive remaining sub-varactor control signals to either the full-scale high value or the full-scale low value of the DAC outputs. Each of the DACs preferably includes a hybrid first order/second order sigma-delta modulator, and in certain embodiments, a NRZ-to-RZ coder circuit, and a linear filter circuit.
1. A circuit comprising:
an input for receiving a first M-bit digital control word;
a plurality K of outputs, each for conveying a respective analog output voltage;
at least a first digital-to-analog converter circuit (DAC) having an input for receiving an N-bit control word, where N is less than M, and having an output for conveying an analog output voltage corresponding to the N-bit control word; and
a multiplexer circuit arranged to couple the output of the first DAC to a selected one of the plurality K of outputs;
wherein a low-order bit portion of the first M-bit digital control word is conveyed as at least a portion of the N-bit control word to the first DAC over at least a range of values for the first M-bit digital control word.
2. The circuit as in claim 1 wherein:
the selected one of the plurality K of outputs is determined by a high-order bit portion of the first M-bit digital control word.
3. The circuit as in claim 1 wherein:
the selected one of the plurality K of outputs is determined by a high-order bit portion of a second digital control word.
4. The circuit as in claim 1 wherein:
the DAC output voltage has a range from a Vmin value to a Vmax value; and
each of the non-selected analog outputs is generated with either the Vmin value or the Vmax value.
5. The circuit as in claim 1 wherein:
the analog outputs to one side of the selected output are generated with the Vmin value, and analog outputs to the other side of the selected output are generated with the Vmax value.
6. The circuit as in claim 1 further comprising:
at least a second digital-to-analog converter circuit (DAC) having an input for receiving a second N-bit control word and having an output for conveying an analog output voltage corresponding to the second N-bit control word; and
a multiplexer circuit arranged to couple the output of the second DAC to a second selected one of the plurality K of outputs;
wherein a low-order bit portion of the first M-bit digital control word is conveyed as at least a portion of the second N-bit control word to the second DAC over at least a range of values for the first M-bit digital control word; and
wherein the first and second N-bit control words are different.
7. A computer-readable medium encoding a circuit as recited in claim 1 .
8. The circuit as in claim 1 further comprising:
a plurality J of digital-to-analog converter circuits (DACs) each having a respective input for receiving a respective N-bit control word, where N is less than M, and having an output for conveying an analog output voltage corresponding thereto;
a multiplexer circuit having a plurality K of outputs, each for conveying a respective analog output voltage, said multiplexer circuit arranged to respectively couple the outputs of the plurality J of DACs to selected ones of the plurality K of outputs, said selection being determined by a high-order bit portion of a second digital control word;
wherein a low-order bit portion of the respective N-bit control word for at least two of the plurality J of DACs is in common over at least a majority of possible values of the first digital control word.
9. The circuit as in claim 8 wherein:
a low-order bit portion of the first M-bit digital control word is conveyed as at least a portion of the respective N-bit control word for at least two of the plurality J of DACs over at least a majority of possible values of the first digital control word.
10. The circuit as in claim 8 further comprising:
wherein each DAC output voltage has a full scale range from a predetermined minimum value to a predetermined maximum value; and
each of the non-selected analog outputs are generated with either the predetermined minimum value or predetermined maximum value.
11. The circuit as in claim 10 further comprising:
wherein analog outputs to one side of the selected outputs are generated with the predetermined maximum value, and analog outputs to the other side of the selected outputs are generated with the predetermined minimum value.
12. The circuit as in claim 8 wherein said multiplexer circuit further comprises:
a plurality K of inputs for receiving a respective one of the plurality of DAC output values;
a pair of inputs for receiving Vmin and Vmax voltage levels, respectively;
wherein said multiplexer circuit is configured to couple the DAC output values to selected ones of the plurality K of outputs, and coupling remaining ones of the plurality K of outputs to either the Vmin level or the Vmax level.
13. The circuit as in claim 12 wherein:
no more than N outputs are at any time at an intermediate voltage between Vmin and Vmax, and each of such N outputs is coupled to a respective output node of an associated one of the plurality J of DACs; and
N is less than J.
14. The circuit as in claim 8 wherein at least one of the selected analog output voltage nodes is at an intermediate voltage between Vmin and Vmax, and is coupled to a respective output node of an associated one of the plurality of DACs.