METHOD FOR THE MANUFACTURE OF A STRAINED SILICON-ON-INSULATOR STRUCTURE
The present invention is directed to a strained silicon on insulator (SSOI) structure having improved surface characteristics, such as reduced roughness, low concentration of LPDs, and lower contamination, and a method for making such a structure.
1 . A method for the preparation of a strained silicon on insulator structure, the method comprising:
forming a relaxed silicon-comprising layer on a surface of a donor wafer;
forming a strained silicon layer on a surface of the relaxed silicon-comprising layer;
forming a dielectric layer on a surface of a handle wafer;
bonding the donor wafer and the handle wafer to form a bonded structure, wherein a bond interface is formed between the strained silicon layer and the dielectric layer;
separating the bonded structure along a separation plane within the relaxed silicon-comprising layer, such that the strained silicon layer on said handle wafer has a residual relaxed silicon-comprising layer on the surface thereof having a thickness of at least about 10 nm; and,
etching the separated handle wafer to substantially remove the residual silicon-comprising layer to expose a surface of the strained silicon layer.
2 . The method of claim 1 wherein the relaxed silicon-comprising layer has a lattice constant substantially different than the lattice constant of pure silicon.
3 . The method of claim 1 , wherein said relaxed silicon-comprising layer comprises SiGe.
4 . The method of claim 3 wherein said etching comprises contacting the SiGe layer with an etchant that has a SiGe:Si selectivity ratio of greater than 3:1.
5 . The method of claim 1 , wherein said etching comprises contacting said residual relaxed silicon-comprising layer with an etchant comprising ammonia.
6 . The method of claim 1 , wherein said etching is performed using megasonic agitation.
7 . The method of claim 1 wherein after said etching, the exposed strained silicon layer surface has a RMS roughness of less than about 1.0 nm.
8 . The method of claim 1 wherein after said etching, the exposed strained silicon layer surface has less than about 0.35 LPDs/cm 2 .
9 . The method of claim 1 wherein after said etching, the exposed strained silicon layer has a Ge concentration of less than about 1×10 10 Ge atoms/cm 2 .
10 . The method of claim 1 wherein ions are implanted into the relaxed silicon-comprising layer substantially along a separation plane at a depth of at least about 10 nm below the surface of the relaxed silicon-comprising layer.
11 . The method of claim 1 wherein said handle wafer and said donor wafer have a diameter of at least about 200 mm.
12 . The method of claim 1 wherein, after etching, said strained silicon layer has a thickness of between about 1 nm and about 100 nm.
13 . A method for the preparation of a strained silicon on insulator structure, the method comprising:
forming a relaxed silicon-comprising layer comprising SiGe having at least about 10% Ge on a surface of a donor wafer;
forming a strained silicon layer on a surface of the relaxed silicon-comprising layer;
forming a dielectric layer on a surface of a handle wafer;
bonding the donor wafer and the handle wafer, wherein a bond interface is formed between the strained silicon layer and the dielectric layer;
separating the bonded structure along a separation plane within the relaxed silicon-comprising layer, such that the strained silicon layer on said handle wafer has a residual relaxed silicon-comprising layer on the surface thereof; and,
etching the separated handle wafer to substantially remove the residual silicon-comprising layer to expose a surface of the strained silicon layer, wherein the etching comprises exposing the handle wafer to an etchant with a selectivity ratio for SiGe:Si of at least about 3:1.
14 . The method of claim 13 wherein said etching comprises contacting said residual relaxed silicon-comprising layer with an etchant comprising ammonia.
15 . The method of claim 13 wherein after said etching, the exposed strained silicon layer surface has a RMS roughness of less than about 1 nm.
16 . The method of claim 13 wherein after said etching, the exposed strained silicon layer surface has less than about 0.35 LPDs/cm 2 .
17 . The method of claim 13 wherein after said etching, the exposed strained silicon layer has a Ge concentration of less than about 1×10 10 Ge atoms/cm 2 .
18 . The method of claim 13 wherein ions are implanted into the relaxed silicon-comprising layer substantially along a separation plane at a depth of at least about 10 nm below the surface of the relaxed silicon-comprising layer.
19 . The method of claim 13 wherein said handle wafer and said donor wafer have a diameter of at least about 200 mm.
20 . The method of claim 13 wherein, after etching, said strained silicon layer has a thickness of between about 1 nm and about 100 nm.
21 . The method of claim 13 , wherein said etching is performed using megasonic agitation.
22 . A silicon on insulator structure comprising a strained silicon layer, a handle wafer, and a dielectric layer therebetween, wherein a surface of the strained silicon layer has less than about 0.35 LPDs/cm 2 .
23 . The silicon on insulator structure of claim 22 the surface of the strained silicon layer has a RMS roughness of less than about 1.0 nm.
24 . The silicon on insulator structure of claim 22 wherein said handle wafer has a diameter of at least about 200 mm.
25 . The silicon on insulator structure of claim 22 wherein said strained silicon layer has a Ge concentration of less than about 1×10 10 Ge atoms/cm 2 .
26 . The silicon on insulator structure of claim 22 wherein the strained silicon layer has a thickness of between about 1 nm and about 100 nm.
27 . A silicon on insulator structure comprising a strained silicon layer, a handle wafer, and a dielectric layer therebetween, wherein the surface of the strained silicon layer has less than about 1×10 10 Ge atoms/cm 2 and an RMS roughness of less than about 1 nm.
28 . The silicon on insulator structure of claim 27 wherein the strained silicon layer surface has less than about 0.35 LPDs/cm 2 .
29 . The silicon on insulator structure of claim 27 wherein said handle wafer has a diameter of at least about 200 mm.
30 . The silicon on insulator structure of claim 27 wherein said strained silicon layer has a Ge concentration of less than about 7.5×10 9 Ge atoms/cm 2 .
31 . The silicon on insulator structure of claim 27 wherein the strained silicon layer has a thickness of between about 1 nm and about 100 nm.