Systems and methods for a turbo low-density parity-check decoder

1. A method for forming, by an apparatus, a parity check matrix, comprising:

generating, by the apparatus, a plurality of cyclic-shifted base matrices, and

generating, by the apparatus, a plurality of square sub-matrices by placing the plurality of cyclic-shifted base matrices and a plurality of zero base matrices as elements of each of the plurality of sub-matrices, wherein placement of the plurality of cyclic-shifted base matrices in each square sub-matrix is defined by a pattern number and an entrance point.

2. The method of claim 1 , further comprising generating a first companion exponential matrix corresponding to the parity check matrix and partitioning the first companion exponential matrix into a plurality of sub-matrices.

3. The method of claim 1 , wherein each of the plurality of cyclic-shifted base matrices comprises a matrix (J) having the following properties: J ∝ =0, J 0 =I, J n =JJ n−1 and J is defined as the left or right of an identity matrix.

4. The method of claim 1 , wherein the sub-matrices correspond to super codes that act as constituent codes.

5. The method of claim 1 , further comprising partitioning each sub-matrix into a plurality of partitioned square sub-matrices.

6. The method of claim 5 , further comprising partitioning each of the plurality of partitioned square sub-matrices into square blocks.

7. The method of claim 5 , wherein each square sub-matrix has one non-zero element per row and one non-zero element per column.

8. The method of claim 5 , wherein each square sub-matrix is constructed using one of a plurality of patterns and one of a plurality of entry points for each of the plurality of patterns.

9. The method of claim 8 , wherein the plurality of patterns comprises 6 patterns.

10. The method of claim 8 , wherein the plurality of entry points comprises 4 entry points.

11. The method of claim 1 , further comprising constructing a second companion exponential matrix corresponding to a second parity check matrix for a second data rate, wherein constructing the second companion exponential matrix comprises forming the second companion exponential matrix from the first companion exponential matrix.

12. The method of claim 11 , wherein forming the second companion exponential matrix from the first companion exponential matrix comprises combining block rows of the first companion exponential matrix.

13. A computer-readable medium encoded with instructions executable by a processor to:

generate a plurality of cyclic-shifted base matrices, and

generate a plurality of square sub-matrices by placing the plurality of cyclic-shifted base matrices and a plurality of zero base matrices as elements of each of the plurality of sub-matrices, wherein placement of the plurality of cyclic-shifted base matrices in each square sub-matrix is defined by a pattern number and an entrance point.

14. An apparatus, comprising:

a parity check matrix generator comprising:

a base-matrix generator configured for generating a plurality of cyclic-shifted base matrices, and

a sub-matrix generator configured for generating a plurality of square sub-matrices by employing the plurality of cyclic-shifted base matrices and a plurality of zero base matrices as elements of each of the plurality of sub-matrices, wherein placement of the plurality of cyclic-shifted base matrices in each square sub-matrix is defined by a pattern number and an entrance point.

15. The apparatus of claim 14 , wherein each of the plurality of square sub-matrices is constructed using one of a plurality of patterns and one of a plurality of entry points for each of the plurality of patterns.

16. The apparatus of claim 14 , wherein each of the plurality of square sub-matrices comprises one non-zero element per row and one non-zero element per column.

17. An LDPC decoder comprises:

a plurality of variable-node processors configured for processing at least one of a set of signals comprising a received signal and a plurality of parity-check messages for generating a plurality of variable-node messages, and

a plurality of parity-check node processors configured for processing the plurality of variable-node messages for updating the plurality of parity-check node messages, the plurality of parity-check node processors further comprising a parity-check matrix processor configured for employing a parity-check matrix characterized by a matrix of square sub-matrices, each of the square sub-matrices comprising a plurality of matrix elements, wherein each of the plurality of matrix elements comprises either a cyclically shifted identity matrix or a zero matrix, the matrix elements being arranged such that each row and each column of each of the square sub-matrices comprises only one non-zero matrix.

18. The LDPC decoder recited in claim 17 , wherein the parity-check matrix processor comprises at least one shift register configured for employing at least one of a set of patterns and at least one of a set of entrance points for generating each of the square sub-matrices.

19. The LDPC decoder recited in claim 17 , wherein the parity-check matrix processor is configured with respect to a plurality of data rates.

20. An LDPC decoding method by an apparatus comprising:

generating, by the apparatus, a plurality of variable-node messages from at least one of a set of signals comprising a received signal and a plurality of parity-check messages, and

updating, by the apparatus, the plurality of parity-check node messages by processing the plurality of variable-node messages, wherein updating further comprises generating a parity-check matrix characterized by a matrix of square sub-matrices, each of the square sub-matrices comprising a plurality of matrix elements, wherein each of the plurality of matrix elements comprises either a cyclically shifted identity matrix or a zero matrix, the matrix elements being arranged such that each row and each column of each of the square sub-matrices comprises only one non-zero matrix.

21. The LDPC decoding method recited in claim 20 , wherein generating the parity-check matrix employs a shift-register process configured for employing at least one of a set of patterns and at least one of a set of entrance points for generating each of the square sub-matrices.

22. The LDPC decoding method recited in claim 20 , wherein generating the parity-check matrix is configured for generating a plurality of parity-check matrices with respect to a plurality of data rates.

23. A computer-readable medium encoded with instructions executable by a processor to:

generate a plurality of variable-node messages from at least one of a set of signals comprising a received signal and a plurality of parity-check messages, and

update the plurality of parity-check node messages by processing the plurality of variable-node messages, wherein updating further comprises generating a parity-check matrix characterized by a matrix of square sub-matrices, each of the square sub-matrices comprising a plurality of matrix elements, wherein each of the plurality of matrix elements comprises either a cyclically shifted identity matrix or a zero matrix, the matrix elements being arranged such that each row and each column of each of the square sub-matrices comprises only one non-zero matrix.

24. An apparatus comprising:

means for generating a plurality of cyclic-shifted base matrices, and

means for generating a plurality of square sub-matrices by placing the plurality of cyclic-shifted base matrices and a plurality of zero base matrices as elements of each of the plurality of sub-matrices, wherein placement of the plurality of cyclic-shifted base matrices in each square sub-matrix is defined by a pattern number and an entrance point.

25. An apparatus comprising:

means for generating a plurality of variable-node messages from at least one of a set of signals comprising a received signal and a plurality of parity-check messages, and

means for updating the plurality of parity-check node messages by processing the plurality of variable-node messages, wherein the updating means further comprises means for generating a parity-check matrix characterized by a matrix of square sub-matrices, each of the square sub-matrices comprising a plurality of matrix elements, wherein each of the plurality of matrix elements comprises either a cyclically shifted identity matrix or a zero matrix, the matrix elements being arranged such that each row and each column of each of the square sub-matrices comprises only one non-zero matrix.